隨著單一晶片上的核心數不斷地增加，晶片網路(Network-on-Chip)成為連結各核心的主要媒介；因此探索晶片網路的設計亦日漸重要。計算機結構研究者通常會建立一對應的模型以研究新的晶片網路架構，並根據其研究結果來實作。記錄導向的模擬為一常用的方式且適於快速地評估及探索新的晶片網路架構；但用來驅動模擬的記錄檔佔用了大量的儲存空間且難以透過網路來傳輸。藉由觀察這些記錄檔通常包含許多重複的特徵，一種基於區間特徵導向的流量產生器Attackboard在最近被提出來解決上述的問題。Attackboard的核心概念為建立記錄溝通特徵的表結構然後用以產生與原記錄檔相似的網路流量；然而Attackboard需要適當調校過的參數以達到可接受的準度，這樣的設計反而限制了其在晶片網路設計探索上的應用性。

在此碩士論文中，我們提出了Attackboard Plus。我們透過新的考量流量相依性的二階表結構來產生晶片網路上的流量，改良了Attackboard的設計，並消除其所需的參數使產生的流量更符合原記錄檔。我們的評估結果顯示Attackboard Plus在只增加些微的儲存空間下達到更佳的準度；而實例研討的結果展示了Attackboard Plus的應用性及潛在的限制。

As the number of cores in a chip increases continuously, Network-on-Chip (NoC) becomes the primary choice for interconnecting the cores. Exploring the design of NoC is hence important. To study a new NoC architecture, architects tend to establish an early-stage model of the interested architecture for evaluation and exploitation of the design space. The results are then used to guide the detailed implementation of the architecture. For fast evaluation and exploitation, trace-driven simulations are often preferred. The problem is that traces require huge space to store and are difficult to transport over the network. By observing that traces usually contain many repetitive, redundant communication patterns, a pattern-driven and interval-based traffic generator, Attackboard, was recently proposed. The idea is to build a small table of communication patterns that can be used to generate traffic to NoC on-the-fly during simulation, whereas the traffic is similar to that generated by the original trace. However, Attackboard requires well-tuned design parameters to obtain an acceptable accuracy compared with the original traces. This therefore limits the applicability of Attackboard.

In this thesis, we propose Attackboard Plus, which uses a new two-level dependency-aware table to generate NoC traffic. It improves Attackboard by eliminating those design parameters and better matching the communication patterns in the original trace. Our evaluations show that Attackboard Plus achieves higher accuracy with slightly higher storage space overhead compared with Attackboard. Case studies on NoC design space exploration show the applicability of Attackboard Plus in general, though some limitations need to be observed.

[1] N. Agarwal, T. Krishna, L.-S. Peh, and N. Jha, “Garnet: A detailed on-chip network
model inside a full-system simulator,” in Proceedings of IEEE International Symposium
on Performance Analysis of Systems and Software, 2009. ISPASS 2009., April 2009,
pp. 33 –42.
[2] M. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu,
A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, “Multifacet’s
general execution-driven multiprocessor simulator (gems) toolset,” SIGARCH
Comput. Archit. News, vol. 33, pp. 92–99, November 2005. [Online]. Available:
http://doi.acm.org/10.1145/1105734.1105747
[3] N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi, and S. Reinhardt, “The m5 simulator:
Modeling networked systems,” in Proc. of the 39th Int’l Symposium on Microarchitecture,
vol. 26, no. 4, 2006, pp. 52–60.
[4] C. Hughes, V. Pai, P. Ranganathan, and S. Adve, “Rsim: Simulating shared-memory
multiprocessors with ilp processors,” Computer, vol. 35, no. 2, pp. 40–49, 2002.
[5] “BookSim 2.0,” Network-on-Chip project at Standford University. [Online]. Available:
https://nocs.stanford.edu
[6] A. B. Kahng, B. Lin, K. Samadi, and R. S. Ramanujam, “Trace-driven optimization
of networks-on-chip configurations,” in Proceedings of the 47th Design Automation
Conference. New York, NY, USA: ACM, 2010, pp. 437–442. [Online]. Available:
http://doi.acm.org/10.1145/1837274.1837384
[7] C. Nitta, M. Farrens, K. Macdonald, and V. Akella, “Inferring packet dependencies
to improve trace based simulation of on-chip networks,” in Proceedings of
the Fifth ACM/IEEE International Symposium on Networks-on-Chip, ser. NOCS
’11. New York, NY, USA: ACM, 2011, pp. 153–160. [Online]. Available:
http://doi.acm.org/10.1145/1999946.1999971
[8] J. Hestness, B. Grot, and S. W. Keckler, “Netrace: Dependency-driven trace-based
network-on-chip simulation,” in Proceedings of the Third International Workshop on
Network on Chip Architectures. New York, NY, USA: ACM, 2010, pp. 31–36. [Online].
Available: http://doi.acm.org/10.1145/1921249.1921258
[9] Y. S.-C. Huang, Y.-C. Chang, T.-C. Tsai, Y.-Y. Chang, and C.-T. King, “Attackboard:
A novel dependency-aware traggic generator for exploring noc design space,” in Proceedings
of the 49th Design Automation Conference (DAC), 2012.
[10] “Intel MPI Benchmarks.” [Online]. Available: http://software.intel.com/enus/
articles/intel-mpi-benchmarks/
[11] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay, M. Reif,
L. Bao, J. Brown, M. Mattina, C.-C. Miao, C. Ramey, D. Wentzlaff, W. Anderson,
E. Berger, N. Fairbanks, D. Khan, F. Montenegro, J. Stickney, and J. Zook, “TILE64
- processor: A 64-core soc with mesh interconnect,” in Proceedings of International
Conference on Solid-State Circuits, 2008. ISSCC 2008., feb. 2008, pp. 88 –598.
[12] Y. S.-C. Huang, J. Ouyang, Y.-Y. Chang, Y. Xie, and C.-T. King, “Tilesim: A scalable
and parallel simulator for noc-centric research,” in Proc. submitted to TVLSI (under
review), 2012.
[13] P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. H˚allberg, J. H¨ogberg,
F. Larsson, A. Moestedt, and B. Werner, “Simics: A full system simulation
platform,” Computer, vol. 35, pp. 50–58, February 2002. [Online]. Available:
http://portal.acm.org/citation.cfm?id=619072.621909
[14] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg,
K. Tiensyrja, and A. Hemani, “A network on chip architecture and design
methodology,” in Proceedings of the IEEE Computer Society Annual Symposium on
VLSI. Washington, DC, USA: IEEE Computer Society, 2002, pp. 117–. [Online].
Available: http://portal.acm.org/citation.cfm?id=876908.881610
[15] M. Burtscher, “Vpc3: a fast and effective trace-compression algorithm,” in Proceedings
of the joint international conference on Measurement and modeling of computer
systems, ser. SIGMETRICS ’04/Performance ’04. New York, NY, USA: ACM, 2004,
pp. 167–176. [Online]. Available: http://doi.acm.org/10.1145/1005686.1005708