處理器與動態記憶體 (DRAM) 的效能落差被稱為記憶體牆 (memory wall)。若研究人員與開發者沒正視此問題，記憶體牆將會日漸嚴重。因此除了加強處理器與記憶體介面外，動態記憶體本身的效能強化也被迫切需要，不論是在原件、電路、或架構上。現在正需要發展新的動態記憶體，於此同時動態記憶體的模型工具 (modeling tools) 在設計探索與效能評估上顯得重要。現有的模型工具在效率上並不足以實際面對記憶體牆，此外這些模型工具缺乏架構彈性 (architecture flexibility) 去探索不同的記憶體架構。在這篇論文中，我們導入組件 (component) 概念且提出以元件為基礎的 (component-based) 動態記憶體模型建立方法。此方法將動態記憶體抽象成框架 (framework)，包含了組件層級的記憶體架構、陣列 (array)、平面圖 (floorplan)、全顆粒 (whole chipe)、以及介面 (interface)。以此抽象化為基礎，我們開發了模型建立工具能夠準確的預測矽面積 (silicon area)、延遲 (delay)、與耗能 (power)，並且擁有高架構彈性與短執行時間。我們的工具被使用在最先進且當前模型無法支援的動態記憶體設計。此外我們改善傳統的電阻電容電壓模型 (RC-delay model and CV-charge models) 來達到更高的準確度，此準確度在實驗中以一商用的雙倍資料速率二代 (DDR2 DRAM) 來驗證。以原件模型為基礎，我們進一步提出一般化架構 (generalized-architecture) 的設計探索方法。此方法中，我們提出變數連結 (variable links) 的概念用來代表變數與變數之間的關係。透過處理變數與變數連結，我們的演算法可以展開設計空間並且降低複雜度。在我們與工研院合作計畫中，此方法被實作來找出全陣列測試晶片 (full array test chip) 的候選者 (candidates)。此測試晶片為一系穿孔堆三維動態記憶體 (TSV-based 3D DRAM)，擁有10ns的低延遲與100GB/s的高頻寬。此外我們也運用這個探索方法來證實某一記憶體架構在寬輸出輸入 (Wide-IO) 介面上，相較於傳統架構擁有較大的發展空間。以組件為基礎的模型建立與架構探索提供系統設計人員可行的方法去辨識更好的動態記憶體系統，進而改善問題的根源 (記憶體牆)。

It is a common understanding that there is a performance gap between the processor and the DRAM in a computer system, which is called the memory wall. The memory wall can become more and more serious if not properly addressed by researchers and practitioners. Therefore, in addition to the improvement of the processor-DRAM interface, there is also drastic need in performance enhancement of the DRAM itself, from device, circuit, to architecture. New DRAM designs need to be developed, and the DRAM modeling tools are crucial to design exploration and evaluation. The existing modeling tools used in design exploration are not efficient enough so far as closing the gap is concerned. Also, there is a lack of flexibility for such tools to explore different architectures. In this thesis, we introduce the notion of component and propose a component-based DRAM modeling method. In this method, we abstracted a DRAM design with a framework, containing the DRAM architecture at the component level, the arrays, the floorplan, the whole chip, and the interface. Based on the abstraction, a modeling tool has been developed to accurately predict the silicon area, delay, and power of the DRAM with high architecture flexibility and short computation time. Our tool has been used for modeling state-of-the-art DRAM designs not supported by the prior works. We also have improved the traditional RC-delay model and CV-charge model to achieve higher accuracy. The modeling accuracy is verified by a commodity DDR2 DRAM in our experiment. With the component-based approach, we also propose a generalized- architecture exploration algorithm, in which we introduce the concept of variable links, representing the relation between the variables. By dealing with the variables and their links, our method can expand the exploration space with the proposed algorithm to reduce the complexity. In our collaboration with ITRI, this method has successfully identified the full array architecture candidates for a DRAM test chip, which is a TSV-based 3D DRAM die (to be used for DRAM die stacking) with a low latency of 10ns and high bandwidth of 100GB/s. We also have used this method to find the array style that has higher potential for the Wide-IO interface than the traditional one. The modeling and exploration approach proposed in this thesis provides system designers with a way to efficiently identify a better DRAM memory system to minimize the memory wall.

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