近幾年來，分離閘快閃式記憶體(Split Gate Flash Memory)已被廣泛地被討論和應用在非揮發性記憶體產品上。就一個先進的快閃式記憶體元件設計來說，高效能(Performance)與高可靠性(Reliability)是兩個主要的考量重點。在過去，分離閘快閃式記憶體的設計改良主要集中在新的元件結構、源極與汲極工程(Source/Drain Engineering)、浮動閘極工程(Floating Gate Engineering)，以及改變元件的操作方式等。本論文針對以浮動閘極工程來改善元件特性的想法，首次提出P型浮動閘極N通道的分離閘快閃式記憶體，除了將浮動閘極摻雜由N型改為P型，還做了不同P型摻雜濃度的比較。根據實驗結果發現，與傳統的N型浮動閘極元件相比較，P型浮動閘極元件擁有較佳的效能與可靠性，換句話說，P型浮動閘極元件具有較低的寫入偏壓、較快的寫入/抹除(Program/Erase)速度；較大的操作區間(Operation Window)、以及較佳的耐久度(Endurance)。最後，此元件已經成功的實現在2Mbits的嵌入式快閃記憶體晶片上，並顯示出P摻雜浮動閘極分離閘快閃式記憶體對90nm嵌入式分離閘快閃記憶體製程以後提供一個可靠的解決方法。

Recently, the Split Gate Flash Memory has been widely discussed and employed in nonvolatile semiconductor memories. For the design of advanced Flash Memories, the performance and reliability are the major concern. In the past, the design of flash memories is mainly focused on the development of the novel cell structure, the source/drain engineering, the floating gate engineering, and the operation methods. In this thesis, we focus on the idea of floating gate engineering to improve the device characteristics, to propose for the first time a new design of P-type floating gate on N channel split gate flash memory. We change the floating gate doping from N-type to P-type with different P-type doping concentration. Based on the experimental results, the N-type floating-gate split gate flash cell has much better performance and reliability than the conventional n-type floating-gate one. In other words, the P-type floating-gate split gate flash cell has faster programming/erasing speed, larger operation window, and better endurance characteristics. Finally, a 2Mbits embedded Flash IP was been successfully implemented statistically compared. The new p-doped split gate structure provides a very promising solution for advanced embedded split-gate Flash memory beyond the 90nm node.

[1] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tahaka, “A New Flash E2PROM Cell Using Triple Polysilicon Technology,” in IEDM Tech. Dig., pp. 464-467, 1984.
[2] A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, “A Novel High-Speed, 5-Volt Programming EPROM Structure with Source-Side Injection, ” in IEDM Tech. Dig., pp. 584-587, 1986.
[3] K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, “A New Flash-Erase EEPROM Cell with A Sidewall Select-Gate on Its Source Side,” in IEDM Tech. Dig., pp. 603-606, 1989.
[4] J. V. Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken, and H. E. Maes “HIMOS - A High Efficiency Flash E2PROM Cell for Embedded Memory Applications,” IEEE Transactions on Electron Devices, vol.40, no.12, pp. 2255-2263, 1993.
[5] W. M. Chen, C. Swift, D. Roberts, K. Forbes, J. Higman, B. Maiti, W. Paulson, and K. T. Chang “A Novel Flash Memory Device with SPlit Gate Source Side Injection and ONO Charge Storage Stack (SPIN),” in Symp. On VLSI Technology, pp. 63-64, 1997.
[6] S. Kianian, A. Levi, D. Lee, Y. W. Hu, “A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E2PROM,” in Symp. On VLSI Technology, pp. 71-72, 1994.
[7] J. F. Van Houdt, G. Groeseneken, and H. E. Maes, “An Analytical Model for the Optimization of Source-Side Injection Flash EEPROM Devices,” IEEE Transactions on Electron Devices, vol.42, no.7, pp. 1314-1320, 1995.
[8] J. F. Van Houdt, D. Wellekens, and G. Groeseneken, “Investigation of the Soft-Write Mechanism in Source-Side Injection Flash EEPROM Devices,” IEEE Electron Device Lett., vol. 16, no.5, pp. 181-183, 1995.
[9] Y. Y. Yao, “A Novel Coupling-Ratios Extraction Technique for Split-Gate Flash Memory Devices,” Master’s dissertation, National Tsing-Hua University, 1999.
[10] W. Z. Wong, “New Bit-Line-Controlled Multi-Level Programming Schemes for Split-Gate Flash Memory,” Master’s dissertation, National Tsing-Hua University, 1999.
[11] Steve S. Chung, C. M. Yih, S. T. Liaw, Z. H. Ho, S. S. Wu, C. J. Lin, D. S. Kuo, and M. S. Liang, “A novel high performance and reliability p-type floating gate n-channel flash EEPROM,” in Symp. On VLSI Technology, pp. 19-20, 1999.
[12] B. C. Wu, H. W. Tsai, S. S. Chung, C. J. Lin, D. S. Kuo, and M. S. Liang, “Improvement of Data Retention in Floating Gate Flash EEPROM’s with P-Doped Floating Gate,” in Solid State Devices and Materials, pp. 640-641, 2003.
[13] Taurus TSUPREM-4 User Guide, Version Y-2006.06, June 2006.
[14] Taurus Medici User Guide, Version Y-2006.06, June 2006.
[15] Taurus Visual User Guide, Version X-2005.10, October 2005.
[16] Y. H. Wang, “Analytical Programming Model and Application of Split Gate Flash Memory,” Doctoral dissertation, National Tsing-Hua University, 2005.
[17] Y. H. Wang, M. C. Wu, C. J. Lin, W. T. Chu, Y. T. Lin, C. S. Wang, and K. Y. Cheng, “An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM,” IEEE Transactions on Electron Devices, vol. 52, no. 3, pp. 385-391, March 2005.
[18] W. T. Chu, H. H. Lin, Y. H. Wang, C. T. Hsieh, H. C. Sung, Y. T. Lin, and C. S. Wang, “High SCR design for one-transistor split-gate full-featured EEPROM,” IEEE Electron Device Lett., vol. 25, no. 7, pp. 498-500, July 2004.
[19] W. D. Brown and J. E. Brewer, “Floating gate nonplanar devices,” in Nonvolatile Semiconductor Memory Technology, 1 ed. Piscataway, NJ: IEEE Press, 1987, ch. 3.
[20] IEEE, IEEE 1005 Standard Definitions and Characterization of Floating Gate Semiconductor Arrays, IEEE Standards Department, Piscataway, 1999.