研究生: |
黃照軒 Huang, Zhao-Xuan |
---|---|
論文名稱: |
一種新型雙重保護的分裂製造防禦模型並同時搭配線段提升演算法下的2.5D積體電路設計 An Innovative Doubly-secure Split Manufacturing Defense Model with Wire Lifting Algorithm for 2.5D IC Technology |
指導教授: |
麥偉基
Mak, Wai-Kei |
口試委員: |
王廷基
WANG, TING-CHI 陳宏明 Chen, Hung-Ming |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 英文 |
論文頁數: | 48 |
中文關鍵詞: | 分裂製造 、線段提升 、2.5D 積體電路設計 |
外文關鍵詞: | Split Manufacturing, Wire Lifting, 2.5D IC Technology |
相關次數: | 點閱:1 下載:0 |
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安全是世界上重要的議題之一。在硬體領域,尤其是積體電路的設計領域中,安全更是不應缺少的一環。隨著科技的進步,當前積體電路設計越來越複雜,在生產成本上也相對大幅增加,這對積體電路設計公司來說是個極大的負擔。因此,將積體電路製造外包給專業製造的第三方是無法避免的趨勢。但是外包生產的行為提供了不受信任的第三方進行各種攻擊的機會,像是透過逆向工程竊取智慧財產權、植入惡意的木馬程式等等。近年來,出於效能考量,半導體產業對2.5D IC產生了極大的興趣。另一方面,我們注意到2.5D 積體電路不僅比傳統的2D設計提供了明顯的良率和功能的改進,同時也提供了加強安全性的機會。
在本篇論文中,我們提出基於2.5D積體電路下的雙重安全分割製造方法,除了將中介層託付給信任廠商製造外,此方法亦將各個晶元進行拆分製造,將生產線的前端與後端託付給不同的代工廠,以及運用我們提出的提升線段演算法。我們的提升線段演算法,能夠提升一些有混淆效果的線段到生產線後端,這樣不但能增加惡意廠商攻擊的難度,又不會對整體晶片的效能造成過多的負擔。在最後的實驗裡,我們運用兩種攻擊方法來攻擊經過我們的方法防禦過的設計來測試我們的方法的防禦強度。實驗結果顯示,在傳統的接近式攻擊以及機器學習的方法下恢復出來的netlist 的準確度都有明顯的降低,並且防禦效果遠大於使用天真方法下的線段提升方法。大大的證明了我們的雙重防禦想法以及提升線段演算法是能有效地增加惡意攻擊者的攻擊難度。
Security is one of the essential terms in our world, especially IC (Integrated Circuit) design with the advancement of technology nodes. Owing to new technological advances, the cost of advanced semiconductor production becomes extremely high and is unaffordable for any single IC design house. Thus, make use of the economics of scale and outsource the IC fabrication to a professional manufacturing third-party is an inevitable trend. However, the outsourcing gives chances for various attacks to be applied by untrusted third-parties, such as IP piracy, IC overbuilding, and Trojan insertion. Among them, IP piracy is one of the most severe problems. Over billions of dollars were lost annually by the semiconductor industry due to intellectual property (IP) infringement.
We have seen that 2.5D integration is a current IC development trend. There are good economic reasons for the huge interest in 2.5D ICs by the semiconductor industry. On the other hand, we note that 2.5D integration does not only provide significant yield and functionality improvements over conventional 2D high-performance SoC designs, it also offers new unique opportunities for security enhancement.
In this thesis, we will investigate the doubly-secure split manufacturing paradigm making use of the structure of 2.5D IC together with the traditional split manufacturing method where the interposers/EMIBs and the upper metal layers of dies, are fabricated by a trusted foundry or in-house. Furthermore, we will effectively incorporate our wire lifting algorithm to lift some key nets to the BEOL layers. In this way, we can sufficiently increase the difficulty for attackers to recover the original netlist while keeping the overall PPA overhead of the chip to a reasonable amount.
In our final experiments, we used two attack methods to verify our defense capability. Experimental results show that the ratio of the nets recovered correctly by the traditional proximity attacks and the machine learning methods has been significantly reduced, which shows that our doubly secure defense and wire lifting algorithm can effectively defend against IP piracy.
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