耗電量資訊對於嵌入式系統是重要且有用的資訊，我們可以利用耗電量資訊來延長系統的使用時間。對於嵌入式系統的幫助十分有用，可以利用這些資訊幫助程式設計者做耗電最佳化設計。功率量測的方法可以利用simulation-based跟measurement-based的方法來獲得。前者為利用功率模型來進行功耗計算的模擬，但是因為模型沒有辦法反映實際硬體的精確功耗在精準度受有所限制。相較之下後者量測的結果就比較接近於實際情況，但是在時間精確度就不若前者。

在這篇論文中，我們使用一個實體的即時嵌入式功耗量測板來量測CPU與記憶體的功率消耗。利用外部的FPGA硬體收集功耗量測模板所收集到的資訊儲存，軟體端便能觀察功率消耗狀態。這樣的設計讓我們可以知道CPU在這段觀察時間內所造成的功率消耗，但並不能了解是哪些原因所造成。所以在論文中我們將這些量測到的資訊與系統上的軟體資訊做結合，試著估算程式在系統上所造成的功率消耗。然而，軟體時間和功率量測系統時間是不同步的，所以當軟體發一個命令給驅動程式控制功率量測系統，驅動程式接收到這個命令與開始控制功率量測系統的時間是不一樣的，所以軟體收集的功率消耗資訊是不正確的。因此，我們提出一個同步化方法去補償驅動程式延遲時間。

除此之外，在軟體與系統驅動程式溝通的過程中，受到作業系統的排成影響，會有一段的延遲，這段延遲也使我們量測到的資訊有誤差，所以我們提出了取樣式的方法，利用Oprofile取樣式的特性，藉由中斷的機制直接觀察CPU的執行狀態並紀錄。用規律的中斷持續的對CPU做取樣，配合功耗量測系統所測量到的結果，利用線性規劃的方法對整個嵌入式系統做進一步的分析，了解程式在系統平台上的功率消耗。

Power consumption is critical constrain for embedded system. In order to provide a criterion
for designers to optimize system power as well as performance, various power evaluation methods
have been proposed. Power evaluation methods can be classified into two groups: simulation-based
and measurement-based. Simulation-based modeling is a good tool for evaluating power due to the
controllability of simulator. However, the simulation accuracy might be questioned since model
might not reflect all the details of actual hardware. Besides, the long simulation time could be
a burden while the extreme accuracy is required. By contrast, the measurement-based method is
closer to reality, but also introduces other issues.

In this thesis, we use a real-time embedded power measurement board, which is developed by
previous work in [1], to measure the power of ARM core and DRAM module on an embedded
system development board. A power collection hardware is designed on FPGA to interface with
the power measurement board. Combining the driver which we develop, the software on ARM
core can access the measured power data real-timely.

To further utilize the real-time power information, in this thesis, we try to map the measured
power data to the corresponding software context on system. One of the challenges we face is the
latency of passing a command to enable power monitor from software. If the command is issued by
a user-level application, it must pass through driver and then to FPGA hardware. From experiment
results, the delay between driver and hardware is almost constant, so we can easily compensate it
by buffering the power data in this constant period. Conversely, the response time from driver to
application is determined by scheduling and varies depending on current system context. To deal
with this difficulty, we propose a sampling-based power monitoring method, based on a system
profile tool, OProfile. Oprofile can record program counter (PC) value periodically by an interrupt

handler which is triggered by performance counter or timer. Finally, due to the limited OProfile
sample rate in our system, an OProfile sample is mapped to multiple samples of measured power.
Trying to rebuild the lost software context, we proposed a linear programming method to analyze
and estimate the power consumption of each profiled function calls.

[1] C.-C. Hs, “Real-Time Power Measurements of an Embedded System”, Master’s thesis, National Tsing-Hua University, Electrical Engineering Department, 2011.
[2] C.-C. Hs, “Power Monitor of Embedded System with Power Signal Compression”, Master’s
thesis, National Tsing-Hua University, Electrical Engineering Department, 2012.
[3] John Levon, Oprofile, 2012, http://oprofile.sourceforge.net/docs/.
[4] Atmel, AT91CAP9A-DK Development Kit User Guide, 2002,
http://www.atmel.com/dyn/resources/prod documents/doc8506.pdf.
[5] ADS805, 2002, http://www.ti.com/lit/gpn/ADS805.
[6] INA195, 2010, http://www.ti.com/lit/gpn/ina195.
[7] Texas Instruments, OMAP35x Evaluation Module (EVM),
2011, http://www.ti.com/tool/tmdsevm3530, http://softwaredl.ti.com/dsps/dsps public sw/psp/LinuxPSP/OMAP 03 00/03 00 01 06/index FDS.html.
[8] Stephen P. Boyd Michael C. Grant, The CVX Users’ Guide, 2012, http://cvxr.com/cvx.
[9] objdump, Objdump, https://sourceware.org/binutils/docs/binutils/objdump.html.
[10] DLP Design, DLP-HS-FPGA2, 2012, http://www.dlpdesign.com/fpga/dlp-hs-fpga2-v21.pdf,
http://www.dlpdesign.com/hfp43/.
[11] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown,
“Mibench: A free, commercially representative embedded benchmark suite”, Workload
Characterization, Annual IEEE International Workshop, vol. 0, pp. 3–14, 2001.