The continuous scaling in CMOS technology is beneficial to design circuits for millimeter-wave wireless communication circuits which extend the data rate by high carrier frequency. This study focuses on designing CMOS high speed phase-locked loop (PLL) and proposing some design technique to overcome general challenges: limiting locking range of frequency dividers and poor performance of VCO.
First, we propose two design techniques to realize high speed and wide locking range frequency divider: Method 1, a Miller divider using gm-boost technique for 24-GHz automotive radar system in TSMC 0.18 µm CMOS was proposed. The proposed technique effectively increases the locking range, resulting in a 1.4□ improvement. As the input signal level increases to 0 dBm, the power consumption becomes 2.76 mW, and the locking range is enhanced to 5.2 GHz from 19.3 GHz to 24.5 GHz. Method 2, using the proposed transformer-injection technique for 60-GHz short distance applications in TSMC 0.13 µm CMOS, the divider demonstrates a wide locking range up to 15.7 GHz from 56.5 GHz to 72.2 GHz. Under the condition of VDD = 0.9 V, the divider can even function with a locking range up to 11.5 GHz and a power dissipation of only 0.81 mW. The proposed technique effectively increases the locking range, resulting in a 3.2□ improvement.
In addition, the VCO and the prescaler are connected directly using the current-reused technique in the proposed design. We combine the two different functional blocks leading to a new configuration with one current path only. Under a VDD of 1.9 V, the structure can function with a power dissipation of only 4.91 mW in TSMC 0.18 µm CMOS. The phase noise is obtained as -113.1 dBc/Hz at 1 MHz offset, which is correspondent to a VCO FOM of -185.8 dBc/Hz.
Finally, in the proposed 10-GHz PLL, the components under the highest speed using the current-reused technique can reduce the power consumption significantly. In the simulation results, the overall power consumption is only 8.36 mW.

由於半導體製程的快速進步，伴隨著資料大量傳遞的需求，使得通訊系統不斷的往高頻邁進。本論文主要目標為利用CMOS製程實現高速系統中的鎖相迴路，提出不同的電路技巧來克服面臨的挑戰：除頻器的除頻範圍不足以及振盪器操作特性不佳等問題。
首先，為實現高速並且寬鎖定範圍之除頻器，本研究提出兩種方法改善可除頻範圍過窄問題：方法一提出運用轉導提升技術之米勒除頻器應用於24-GHz雷達系統，以TSMC 0.18-µm CMOS製程實現，量測結果顯示，操作於2.76-mW之功耗時，此技術可較傳統米勒除頻器提升1.4倍可除頻率，範圍為19.3-GHz至24.5-GHz。方法二提出變壓器注入技術之米勒除頻器應用於60-GHz短距離傳輸，以TSMC 0.13- µm CMOS製程實現，量測結果顯示，非自振情況下，能操作於0.81-mW之低功耗，並且擁有11.5-GHz的鎖定範圍；而改變偏壓令功率加大至3.78-mW時，在0 dBm之輸入功率下，可除頻頻率加大為56.5-GHz至72.2-GHz，擁有15.7-GHz的鎖定範圍，此技術可較傳統米勒除頻器提升3.2倍可除頻率。
接著，針對高速操作之振盪器與第一級除頻器，運用電流重複運用技術，只使用一路電流結合共振腔振盪器與電流模式邏輯閘除頻器成一個新單元。此設計使用TSMC 0.18-µm CMOS當供應電壓為1.9V時，總功率消耗為3.9-mW。離主頻1 MHz之相位雜訊為-113.8 dBc/Hz，相對應之FOM為-185.8 dBc/Hz。
最後，將鎖相迴路中最高速之區塊使用上述電流重複運用技術實現10-GHz達到低功率設計。模擬結果顯示，整個鎖相迴路只消耗8.36 mW的功耗。

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