在等效氧化層厚度的微縮需求下，二氧化鉿的k值逐漸無法滿足現今MOSFET微縮趨勢，相對於使用單層二氧化鉿介電層，使用較高k值的介電層堆疊有較好的電特性，然而，如果使用更高k值的介電材料會造成載子遷移率下降的問題，這是使用更高k值的介電材料所帶來的挑戰。介面層與介電層之介面會因介電材料而受影響，有些介電材料可能會與介面層反應產生介電常數較小的矽化物，使得等效氧化層厚度提升，以及劣化介面品質，讓閘極漏電流增加。此外，介電層與金屬閘極之介面影響也是很重要，可能會因介電層所產生的氧空缺還有介面偶極的改變，而導致臨界電壓偏移以及可靠度的問題，因此多層介電層堆疊結構鰭式電晶體將在此論文中提出。
第一部分，在原子層沉積系統(ALD)機台以不同條件的control (HfO2)、兩層結構Bilayer (ZrO2/HfO2)、Hf-rich trilayer以及Zr-rich trilayer (HfO2/ZrO2/HfO2)介電層堆疊，藉提高介電層之介電系數，達到抑制等效氧化層厚度的效果，而底層的HfO2介電層堆疊可以避免二氧化鋯穿隧，並透過不同的結構堆疊，觀察介電層對金屬閘極之介面電性差異。實驗結果可以發現，Zr-rich trilayer結構之EOT達到了6.9 Å，而且透過ZrO2較高的k值，可以提升汲極電流。另外，我們也發現三層結構堆疊有較優的Stress induced threshold voltage shift。
第二部分，延續上一部分的結果，利用二氧化鈦更高的k值，希望可以得到更薄的EOT，且提升可靠度，並比較介電層對金屬閘極之介面影響。由實驗結果可以得知含有TiO2的閘極介電層堆疊元件有較好的可靠度，以及大幅提升汲極電流。而三層結構可以改善閘極漏電流、可靠度以及高電場下載子遷移率衰退的缺點。

As equivalent oxide thickness (EOT) scaled down, the k-value of HfO2 is not high enough to continue the downscaling of advanced MOSFETs. Compared to single HfO2 dielectric, the stacked gate dielectric with higher dielectric constant (k-value) exhibits superior performance. However, the carrier mobility degradation may be caused by higher k-value dielectric material. This is the challenge caused by using higher k-value gate dielectric. The interface between interfacial layer and high-k dielectric is influenced by dielectric materials. The interface between interfacial layer and high-k dielectric is influenced by dielectric materials. A lower k-value of silicide may be easily formed at interfacial layer and high-k interface, which may induce the increases of EOT and Jg. On the other hand, the interface between gate electrode and high-k dielectric is also very important due to the generation of oxygen vacancy and the change of interface dipole, which may induce threshold voltage shifts and some reliability problem. Therefore, a novel multilayer dielectric gate stack is proposed on FinFET in this thesis
In the first part, gate dielectrics with control (HfO2), bilayer (ZrO2/HfO2), Hf-rich trilayer and Zr-rich trilayer (HfO2/ZrO2/HfO2) are in-situ deposited in atomic layer deposition (ALD), respectively. ZrO2 with a higher k-value was used to reduce the EOT. ZrO2 diffusion can be suppressed by a bottom layer of HfO2. Effects of interface between gate dielectric and metal gate on electrical characteristics of FinFET are studied by different stacked gate dielectric. Results show that the EOT of device with Zr-rich trilayer stack is scaled down to 6.9 Å. The drain current is improved by Zr-containing gate stacks due to its higher k-value. Furthermore, the stress induced threshold voltage shifts are lower for sample with trilayer stacked gate dielectric.
In the second part, HfO2 and TiO2 stack are proposed as gate dielectric to reduce EOT and improve reliability of FinFET. The better reliability and higher on current are achieved by bilayer and trilayer gate dielectric. In addition, the reduced gate leakage current, better reliability and the improvement of mobility degradation at high electric field are obtained for FinFET with trilayer stack.

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