近年來，三維立體晶片整合(3D Integration)是一項相當具有發展潛力的一項關鍵技術，不但可提高系統式封裝的密度，並可達到異質晶片之整合。其中矽晶穿孔(Through Silicon Via, TSV)結構是用以連結不同層之晶片的內部線路，但是晶片之散熱方式及其TSV材料間的熱膨脹係數不匹配，所以在往覆的溫度熱循環測試之負載之下，會有應力集中(Stress Concentration)的現象發生，導致結構發生破壞行為降低電子元件的可靠度。
本論文利用有限元素軟體ANSYS®進行TSV結構之力學模擬分析，針對具有矽晶穿孔之陣列及TSV接合部位的晶片堆疊結構受到加速熱循環測試極限溫度附載時之熱應力模擬，針對其結構幾何參數進行探討並分析其應力發生原因。另外，並將參數化分析的結果搭配實驗設計中的因子設計法(Factorial Designs)，進行該結構的變異數分析，找出影響應力最顯著之設計因子。
根據分析之結果，TSV陣列熱應力模擬結果顯示，在TSV空孔邊緣之金屬鎳會受到熱膨脹而拉伸或是收縮，使得此處產生最大應力。另外，在二氧化矽與矽的接面也會有應力產生，可能會使材料間發生脫層。此外在TSV參數分析中，減小墊片尺寸最能有效降低熱應力並且根據模擬結果也發現，降低填孔直徑比例與增加TSV之間距也可有效降低其應力。利用以上結果，本研究將得到在TSV陣列中之熱應力分布情形，並可用以找出TSV結構發生破壞的位置。

Recently 3D chip integration is an emerging technology. It can achieve high package density and integration of heterogeneous chip. Through silicon via provides vertical interconnections between stacking dies in 3D chip integration. However, there are still some challenges for this technology such as heat dissipation of 3D chip and large differences of coefficient of thermal expansion (CTE) in TSV structure. Due to the large thermal mismatch, the thermal stress at the interface of materials may result in the reliability problem of chip.
In this study, the thermal-mechanical stress distribution of a three dimensional TSV array model and bonding pad of TSV structure under the condition of accelerated thermal cycling loading is investigated by finite element analysis software-ANSYS®. Furthermore, the effect of geometry parameter of TSV to thermal stress is studied and analyzed by factorial designs and sensitivity analysis. According to the simulation result, the nickel at the TSV structure annular edges is stretched at 125 ﾟC and contracted at -40 ﾟC by the thermo expansion of other material, so the maximum thermal stress occurs at the nickel. Besides, the stress also occurs at the interface of silicon and silicon dioxide which may result in failure or delamination of TSV pads. In addition to, the parametric sensitivity analysis result shows that reducing the pad diameter is the most effective way to lower the thermal stress. Reduce the diameter ratio and increase the pitch between TSV can also lower the thermal stress. With these results, this study helps to obtain a clear thermal stress distribution of TSV array and possible failure regions in the TSV structure.

[1]Gordon E. Moore, ‘‘Cramming More Components onto Integrated Circuits,’’ Electronics, Vol. 38, No. 8, pp. 114-117, 1965
[2]Wolfgang Arden, Michel Brillouët, Patrick Cogez, and Mart Graef, Bert Huizing, Reinhard Mahnkopf, ‘‘More than Moore White Paper by the IRC,’’ ITRS, 2009
[3]Jian-Qiang Lu,‘‘3-D Hyper integration and Packaging Technologies for Micro-Nano Systems,’’ Proceedings of the IEEE, Vol. 97, pp. 18–30, 2009.
[4]‘‘ITRS Report of Assembly and Packaging,’’ ITRS, 2009
[5]Rajen Chanchani, ‘‘3D Integration Technologies – An Overview,’’ Materials for Advanced Packaging, pp.2-5, 2009
[6]Masahiro Sekiguchi, Hideo Numata, Ninao Sato, Tatsuhiko Shirakawa, Mie Matsuo, Hiroshi Yoshikawa, Mitsuhiko Yanagida, Hideo Nakayoshi and Kenji Takahashi, ‘‘Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor,’’ Electronic Components and Technology Conference, pp. 1367-1374, 2006
[7]Tzu-Ying Kuo, Shu-Ming Chang, Ying-Ching Shih, Chia-Wen Chiang, Chao-Kai Hsu, Ching Kuan Lee, Chun-Te Lin, Yu-Hua Chen, Wei-Chung Lo, ‘‘Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost,’’ Electronic Components and Technology Conference, pp. 853-858, 2008
[8]Makoto Motoyoshi, ‘‘ Through-Silicon Via (TSV),’’ Proceedings of the IEEE, Vol.97, pp. 43-48, 2009
[9]Philip Garrou, Christopher Bower, and Peter Ramm, ‘‘Handbook of 3D Integration : Technology and Applications of 3D Integrated Circuits,’’ Vol. 1, pp. 35-37, 2008
[10]N Ranganathan, K Prasad, N Balasubramanian, and K L Pey, ‘‘A Study of Thermo-mechanical stress and Its Impact on Through-Silicon Vias, ’’Journal of Micromechanics and Microengineering, Vol. 18, 075018, 2008
[11]Chao Wei Tang, Hong Tsu Young, and Kuan Ming Li, ‘‘Innovative through-silicon-via formation approach for wafer-level packaging applications, ’’ Journal of Micromechanics and Microengineering, Vol. 22, 045019, 2012
[12]Suk-Kyu Ryu, Kuan-Hsun Lu, Xuefeng Zhang, Jang-Hi Im, Paul S. Ho, and Rui Huang, ‘‘Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D Interconnects,’’ Device and Materials Reliability, IEEE Transactions, Vol. 11, pp. 35-43, 2011
[13]http://en.wikipedia.org/wiki/Bathtub_curve
[14]‘‘JESD22-A104D’’, JEDEC
[15]Philip Garrou, Christopher Bower, Peter Ramm‘‘Handbook of 3D Integration : Technology and Applications of 3D Integrated Circuits,’’ Vol. 2, pp. 308-317, 2008
[16]Daryl L. Logan, ‘‘A First Course in the Finite Element Method,’’ 4, Prentice Hall PTR, pp. 4-131, 2003
[17] A. C. Ugural, Saul K. Fenster, ‘‘Advanced strength and applied elasticity,’’ 4, Cengage Learning, pp. 14-82, 2007
[18]R. D. Cook, D. S. Markus, and M. E. Plesha, Concepts and Applications of Finite Element Analysis, 4th, John Wiley & Sons, Inc., New York, 2002
[19]A. C. Ugural, Saul K. Fenster, ‘‘Advanced strength and applied elasticity,’’ 4, Cengage Learning, pp. 145-175, 2007
[20]ANSYS User’s Manual, ANSYS Inc. Company
[21]Douglas C. Montgomery, 黎正中譯, ‘‘實驗設計與分析,’’ 7, 高力圖書, pp. 187-277, 2012
[22]Cheryl S. Selvanayagam, John H. Lau, Xiaowu Zhang, S. K.W. Seah, Kripesh Vaidyanathan and T. C. Chai, ‘‘Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps,’’ Electronic Components and Technology Conference, pp. 1073-1081, 2008
[23]Zhaohui Chen, Xiaohui Song, Sheng Liu, ‘‘Thermo-mechanical Characterization of Copper Filled and Polymer Filled TSVs considering Nonlinear Material Behaviors,’’ Electronic Components and Technology Conference, pp. 1374-1380, 2009
[24]P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, B. Wunderle, B. Michel, ‘‘Through Silicon Via Technology — Processes and Eeliability for Wafer-level 3D System Integration,’’ Electronic Components and Technology Conference, pp. 841-846, 2008
[25]Xi Liu, Qiao Chen, Pradeep Dixit, Ritwik Chatterjee, Rao R. Tummala, and Suresh K. Sitaraman,‘‘Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV),’’ Electronic Components and Technology Conference, pp. 624-629, 2009
[26]Kuan H. Lu, Suk-Kyu Ryu, Qiu Zhao, Xuefeng Zhang, Jay Im, Rui Huang, and Paul S. Ho, ‘‘Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects,’’ Electronic Components and Technology Conference, pp. 40-45, 2010
[27]Leila J. Ladani, ‘‘Numerical Analysis of Thermo-mechanical Reliability of Through Silicon Vias (TSVs) and Solder Interconnects in 3-Dimensional Integrated Circuits,’’ Journal of Microelectronic Engineering, Vol. 87, pp. 208-215, 2010
[28]C. J. Wu, M. C. Hsieh, K. N. Chiang, ‘‘Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via,’’ Microelectronic Engineering, Vol. 87, pp. 505-509, 2010
[29]Chunbo Zhang and Leijun Li, ‘‘Characterization and Design of Through-SiliconVia Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling, ’’IEEE Transactions on electron devices, Vol. 58, pp. 279-287, 2011
[30]Sun-Rong Jan, Tien-Pei Chou, Che-Yu Yeh, Chee Wee Liu, Robert V. Goldstein, Valentin A. Gorodtsov, and Pavel S. Shushpannikov, ‘‘A Compact Analytic Model of the Strain Field Induced by Through Silicon Vias,’’ IEEE Transactions on Electron Devices, Vol. 59, pp. 777-782, 2012
[31]Moongon Jung, David Z. Pan, and Sung Kyu Lim, ‘‘Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs,’’ DAC12 Proceedings of the 49th Annual Design Automation Conference, Vol. 59, pp. 317-326, 2012
[32]Choa Sung-Hoon, Song Cha Gyu, Lee Haeng Soo,‘‘Investigation of durability of TSV interconnect by numerical thermal fatigue analysis,’’ International journal of precision engineering and manufacturing, Vol. 12, pp. 589-596, 2011