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研究生： 陳彥廷
Chen, Yen-Ting
論文名稱： K頻段之SiGe HBT功率放大器與採用傳輸線型互感功率整合5.5GHz/K頻段之CMOS功率放大器
Design of K-band SiGe HBT Power Amplifier and 5.5GHz/K-band CMOS Power Amplifiers using Transmission-Line Transformer Power Combiners
指導教授： 徐碩鴻
Hsu, Shao Hung
口試委員: 孟慶宗
Meng, Ching-Tzung
劉怡君
Liu, Yi-Jun
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2017
畢業學年度： 106
語文別： 英文
論文頁數： 76
中文關鍵詞： 功率放大器 、傳輸線型互感 、高功率
外文關鍵詞： Transmission line transformer
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    • 近年，隨著無線通訊傳輸技術的日新月異，行動通訊以及無線通訊大量資料傳輸的需求有爆炸性的成長。此篇論文探討了射頻功率放大器的研究，分別使用以下三種不同的製程，包括了SiGe HBT，180 nm CMOS 和 90 nm CMOS。
    首先，對於功率放大器的研究動機以及基本介紹會在第一部分討論。在第二章節，功率放大器基本概念以及重要設計考量將會在此章節有所討論，其中包含了一些功率放大器設計時需要考量的重要參數，例如輸出功率、效率、線性度等等。另外，傳統的互感以及傳輸線型互感的設計都會在此章節有所討論。第三章至第五章這幾個章節則會分別討論三個功率放大器電路的設計流程以及細節，包含了整體電路架構、電晶體大小、互感的設計以及模擬和量測結果都會有詳盡的解說。
    第一個功率放大器為K-Band SiGe HBT差動功率放大器。本顆晶片採用了傳輸線型的互感來完成級間的匹配而減少損耗，本顆功率放大器在操作頻率為21 GHz時能夠達到最大輸出功率P_sat=11.6 dBm 以及8 dB的功率增益。整顆晶片尺寸為 1.32×0.75 〖mm〗^2.
    第二個功率放大器電路為一個5.5 GHz的高功率輸出窄頻功率放大器採用傳輸線型互感設計之功率整合。藉由採用兩路的傳輸線型互感功率整合，此電路能夠達到最高輸出功率21.8 dBm，功率增益7.2 dB以及peak PAE = 11.3 %的特性。整顆晶片尺寸為 1.875×1.06 〖mm〗^2.
    最後一個電路為一個K-Band寬頻差動功率放大器採用傳輸線型互感設計之功率整合。藉由採用四路的傳輸線型互感功率整合，此電路於K-Band模擬能夠達到輸出功率24 dBm，以及在19 GHz 有22 dB的功率增益和 peak PAE = 22.62 %的特性。整顆晶片尺寸為 1.659×0.711 〖mm〗^2.

    With the rapid development of wireless communication technology, the demand of mobile communication and high data rate wireless communications is blooming in recent years.This thesis presents the research on RF power amplifier using three different IC technologies, including SiGe HBT, 180 nm CMOS and 90 nm CMOS. The introduction and motivation of the PA design are discussed in the beginning. Chapter II presents the basic concepts of power amplifier, including some important parameters. From chapter III to chapter IV, three designed Pas are presented in detail, including the proposed circuit of each design, size of the transistor, design of the transformers and the simulation and measurement results.
    The first PA, a K-Band SiGe HBT differential power amplifier is presented. By applying the transmission line transformer for the inter-stage matching, the designed PA can achieve maximum output power P_sat about 11.6 dBm and gain of 8 dB at the frequency of 21 GHz with the chip size of 1.32×0.75 〖mm〗^2.
    The second one, we realized a 5.5 GHz high output power narrow band differential power amplifier with a proposed TLT power combiner. By applying the transmission line transformer into the power combiner, the innovative idea accomplishes a 2-ways TLT power combiner. The proposed PA can achieve P_sat about 21.8 dBm, gain of 7.2 dB and peak PAE equals to 11.3 % with the chip size of 1.875×1.06 〖mm〗^2.
    At last, a k-band wideband differential power amplifier with 4-way TLT power combining is presented. The designed PA can achieve about 24 dBm around k-band with the peak PAE = 22.62 % and the gain = 22 dB at the 19 GHz in simulation. By the proposed layout technique, we reduce the chip size to 1.659×0.711 〖mm〗^2.

    ABSTRACT i 摘要 i TABLE OF CONTENTS iii LIST OF FIGURES vi LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 3 1.3 Thesis Organiztion 4 Chapter 2 Basic Concepts of Power Amplifier 5 2.1 Introduction 5 2.2 Important Parameters 6 2.2.1 Output Power 6 A. Saturation Power 6 B. 1-dB Compression Point 6 2.2.2 Efficiency 7 A. Drain Efficiency 8 B. Power-Added-Efficiency 8 2.2.3 Linearity 9 2.3 Loadline Theory and Optimal Impedance 10 2.4 Classification of Power Amplifier 11 2.5 Introduction to Transformer 13 2.5.1 Magnetic Coupling Transformer 14 2.5.2 Transmission Line Transformer 16 Chapter 3 Design of K-Band SiGe HBT Differential Power Amplifier 19 3.1 Introduction 19 3.2 Design of K-band Differentail Power Amplifier 19 3.2.1 Proposed Circuit 19 3.2.2 Design of Transistor Cell 21 3.2.3 Design of Transformer 22 A. Input Transformer 22 B. Inter-stage Transformer 24 C. Output Transformer 26 3.3 Simulation and Measurement Results 27 3.3.1 Layout Implementation 28 3.3.2 Small-signal Measurement Results 29 3.3.3 Large-signal Measurement Results 31 Chapter 4 Design of 5.5 GHz High Output Power Narrow Banb Differential Power Amplifier with Transmission Line Transformer Power Combine……………………………………………………………………………….35 4.1 Introduction 34 4.2 Design of 5.5 GHz Differentail Power Amplifier 36 4.2.1 Proposed Circuit 35 4.2.2 Design of Transistor Cell 37 4.2.3 Design of Transformer 38 A. Input Transformer 38 B. Output Transformer 40 4.3 Simulation and Measurement Results 42 4.3.1 Layout Implementation 42 4.3.2 Small-signal Measurement Results 43 4.3.3 Large-signal Measurement Results 46 Chapter 5 Design of K-Band Wideband Differential Power Amplifier with TLT Power Combine ………………………………………………………….........51 5.1 Introduction 51 5.2 Design of 5.5 GHz Differentail Power Amplifier 52 5.2.1 Proposed Circuit 52 5.2.2 Design of Transistor Cell 53 5.2.3 Design of Transformer 54 A. Input Transformer 54 B. Inter-stage Transformer (I) 56 C. Inter-stage Transformer (II) 58 D. Output Transformer 59 5.3 Simulation and Measurement Results 61 5.3.1 Layout Implementation 61 5.3.2 Small-signal Measuement Results 63 5.3.3 Large-signal Measurement Results 67 Chapter 6 Conclusion and Future Work 72 References 73 LIST OF FIGURES Fig. 1.1 Transceiver circuit of the wireless communication system 1 Fig. 2.1 Transceiver for wireless communication system 5 Fig. 2.2 Definition of 1-dB compression point and saturation power 7 Fig. 2.3 Definition of the third-order interception point 9 Fig. 2.4 Conceptual I/V curve of a source loaded with different resistances. 10 Fig. 2.5 The effects on the load line with parasitic capacitance in MOS 11 Fig. 2.6 Classification of Power Amplifier 12 Fig. 2.7 Operation of switch mode PA 13 Fig. 2.8 (a) Model of magnetic coupling transformer. (b) The equivalent circuit of magnetic coupling transformer 14 Fig. 2.9 (a) Inter-wound (Frlan) winding. (b) Overlay (Finlay) winding 15 Fig. 2.10 (a) Ruthoff type TLT. (b) Guanella type TLT 16 Fig. 2.11 Guanella type TLT with differential input and output 17 Fig. 3.1 Circuit structure of the designed k-band differential PA 20 Fig. 3.2 (a) Power stage of designed PA. (b) Drive stage of the designed PA 21 Fig. 3.3 (a) Power stage of designed PA. (b) Drive stage of the designed PA 22 Fig. 3.4 (a) Top view of input transformer (b) Side and down view of input transformer 23 Fig. 3.5 Inductance and quality factor of primary and secondary inductor of input transformer. 23 Fig. 3.6 Loss of the designed input transformer 24 Fig. 3.7 (a) Top view of inter-stage transformer (b) Side and down view of inter-stage transformer 25 Fig. 3.8 Loss of the designed inter-stage transformer 25 Fig. 3.9 (a) Top view of output-stage transformer (b) Side and down view of output-stage transformer 26 Fig. 3.10 Inductance and quality factor of primary and secondary inductor of output transformer 26 Fig. 3.11 Loss of the designed output-stage transformer 27 Fig. 3.12 Chip photo of the designed PA 28 Fig. 3.13 Chip photo of the designed PA with DC and RF probes 28 Fig. 3.14 Simulation and measurement results of |S_11 | from 0-45 GHz 29 Fig. 3.15 Simulation and measurement results of |S_12 | from 0-45 GHz 29 Fig. 3.16 Simulation and measurement results of |S_21 | from 0-45 GHz 30 Fig. 3.17 Simulation and measurement results of |S_22 | from 0-45 GHz 30 Fig. 3.18 Simulation and measurement results of S-parameters from 0-45 GHz 31 Fig. 3.19 Large-signal simulation and measurement results of designed PA at 21 GHz 32 Fig. 3.20 Large-signal simulation and measurement results of designed PA at 22 GHz 32 Fig. 3.21 Measured P_sat and Gain from 19 to 25 GHz 33 Fig. 4.1 Circuit structure of the designed 5.5 GHz 2-ways TLT power combiner PA 36 Fig. 4.2 (a) Drive stage of designed PA. (b) Power stage of the designed PA 37 Fig. 4.3 (a) Top view of input transformer (b) Side and down view of input transformer 39 Fig. 4.4 Inductance and quality factor of primary and secondary inductor of input transformer 39 Fig. 4.5 Loss of the designed input transformer 40 Fig. 4.6 (a) Top view of input transformer (b) Side and down view of input transformer 41 Fig. 4.7 Loss of the designed transmission line transformer 41 Fig. 4.8 (a) Top view of designed TLT power combiner (b) Side and down view of designed TLT power combiner 42 Fig. 4.9 Chip photo of the designed PA 43 Fig. 4.10 Chip photo of the designed PA with DC and RF probes 43 Fig. 4.11 Simulation and measurement results of |S_11 | 44 Fig. 4.12 Simulation and measurement results of |S_12 | 44 Fig. 4.13 Simulation and measurement results of |S_21 | 45 Fig. 4.14 Simulation and measurement results of |S_22 | 45 Fig. 4.15 Simulation and measurement results of S-parameters 46 Fig. 4.16 Large-signal simulation and measurement results of designed PA at 4.9 GHz 47 Fig. 4.17 Large-signal simulation and measurement results of designed PA at 5.1 GHz 47 Fig. 4.18 Large-signal simulation and measurement results of designed PA at 5.3 GHz 48 Fig. 4.19 Large-signal simulation and measurement results of designed PA at 5.5 GHz 48 Fig. 4.20 Large-signal simulation and measurement results of designed PA at 5.7 GHz 49 Fig. 4.21 Measured P_sat and Gain from 4.9 to 5.7 GHz 49 Fig. 5.1 Circuit structure of the designed k-band 4-ways TLT power combiner PA 53 Fig. 5.2 (a) Power stage of designed PA. (b) Drive stage of the designed PA 54 Fig. 5.3 (a) Top view of input transformer (b) Side and down view of input transformer 55 Fig. 5.4 Inductance and quality factor of primary and secondary inductor of input transformer 55 Fig. 5.5 Loss of the designed input transformer 56 Fig. 5.6 (a) Top view of inter-stage transformer (b) Side and down view of inter-stage transformer 56 Fig. 5.7 Inductance and quality factor of primary and secondary inductor of inter-stage transformer 57 Fig. 5.8 Loss of the designed inter-stage transformer 57 Fig. 5.9 (a) Top view of inter-stage transformer (b) Side and down view of inter-stage transformer 58 Fig. 5.10 Inductance and quality factor of primary and secondary inductor of inter-stage transformer 58 Fig. 5.11 Loss of the designed inter-stage transformer 59 Fig. 5.12 (a) Top view of TLT (b) Side and down view of TLT 60 Fig. 5.13 Loss of the designed TLT 60 Fig. 5.14 4-way TLT power combiner 61 Fig. 5.15 Chip photo of the designed PA 62 Fig. 5.16 Chip photo of the designed PA with DC and RF probes 62 Fig. 5.17 Layout of power combiner PAs 63 Fig. 5.18 Simulation results of S-parameters from 0-45 GHz 64 Fig. 5.19 Simulation and measurement results of |S_11 | 64 Fig. 5.20 Simulation and measurement results of |S_12 | 65 Fig. 5.21 Simulation and measurement results of |S_21 | 65 Fig. 5.22 Simulation and measurement results of |S_22 | 66 Fig. 5.23 Simulation and measurement results of S-parameters from 0-45 GHz 66 Fig. 5.24 Adjusted simulation and measurement results of S-parameters from 0-45 GHz 67 Fig. 5.25 Large-signal simulation results of designed PA at 19 GHz 68 Fig. 5.26 Large-signal simulation results of designed PA at 22 GHz 68 Fig. 5.27 Large-signal simulation results of designed PA at 25 GHz 69 Fig. 5.28 Large-signal simulation results of designed PA at 28 GHz 69 Fig. 5.29 Large-signal simulation and measurement results of designed PA at 21 GHz 70 Fig. 5.30 Simulated P_sat and Gain from 18 to 29 GHz 70 LIST OF TABLES Table 1 1 Summary of published k-band power amplifiers 3 Table 2 1 Classification of PAs in term of conduction angle and biasing point 12 Table 2 2 Classification of PAs in term of efficiency 13 Table 3 1 Summary of the design parameters of proposed PA 20 Table 3 2 Comparison table with referenced k-band PA 33 Table 4 1 Summary of the design parameters of proposed PA 37 Table 4 2 Comparison table with referenced PA 50 Table 5-1 Summary of the design parameters of proposed PA 52 Table 5-2 Comparison table with referenced k-band PA 71

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