本論文提出一種相容於邏輯製程，可在三維空間堆疊的新型高密度電阻式記憶體，此元件隨著製程演進具有高微縮性以及堆疊特性，並分別在以鋁為金屬接線材料以及以銅為金屬接線材料的後端製程上成功驗證。此種新型電阻式記憶體可達成高記憶體容量與單晶片系統(SoC)設計的需求。
在鋁製程底下，電阻性記憶薄膜可以被堆疊在不同金屬層之間，其成分為鈦氮氧化物(TiON)，其中鈦(Ti)與氮化鈦(TiN)在製程中被廣泛用來當作防止鋁銅合金擴散的阻擋層以及鎢的附著層材料；在雙鑲嵌銅金屬接線製程底下，此電阻性記憶薄膜由鉭氮氧化物(TaON)組成，其中鉭(Ta)與氮化鉭(TaN)也同樣在後端製程中被用作防止銅擴散的阻擋層材料。記憶薄膜的上下層電極則以垂直正交的方式連接成高密度的交叉點式(Cross-point)陣列。
利用不同元件佈局設計，可在垂直方向以串聯方式，形成鉭氧化物(TaO)二極體驅動之電阻式記憶體 (1D1R)的結構，此種1D1R記憶體在交叉點式記憶體陣列上能夠有效抑制潛電流的發生。相較於由金氧半電晶體或雙極性接面電晶體與電阻式記憶體結合的二維平面記憶體陣列，後端邏輯製程步驟相對簡單、可多層堆疊且低成本，此種獨特的製程優勢使得三維空間堆疊的新型通孔電阻式記憶體具有相當大的潛力作為高密度嵌入式非揮發性記憶體的應用。

In this thesis, a high density 3D-stacked Via RRAM compatible with CMOS logic process without any extra mask has been proposed. This novel resistive-memory device has been demonstrated successfully both in the Al-based backend process and the Cu-based backend process.
Under the Al-based backend process, RRAM consists of TiON is fabricated between W top electrode and AlCu bottom electrode. Ti and TiN are commonly adopted as the barrier layer to prevent the diffusion of AlCu alloy. TMO layer is automatically formed during BEOL manufacturing steps. In the Cu dual damascene backend process, RRAM consists of TaON is stacked between two Cu electrodes. Similarly, Ta and TaN are usually adopted as the barrier layer to prevent Cu diffusion. By arranging WLs and BLs in the orthogonal direction, a high-density and cross-point RRAM array was successfully demonstrated.
A vertical 1D1R bit cell driven by a TaO-based oxide diode is fabricated by layout adjustments. The influence of sneak current path in the cross-point array can be severely suppressed by adopting 1D1R cell structure. Comparing 1T1R and 1BJT+1R cells, the Via RRAM 1D1R cell is multi-layer stackable, and lower cost. We believe that the novel 3D-stacked Via RRAM has high potential in the applications of storage-class embedded NVM.

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