Through-Silicon-Via (TSV), which connects dies in vertical direction, is a critical design issue of three-dimensional integrated circuit (3D IC). Because a single TSV defect leads to die failure, redundant TSVs are added to enhance the overall yield. We propose a new redundant TSV architecture called TSV-grid. This architecture is especially suitable for applications that need a large number of TSVs using a process that has high TSV failure rate. We also propose a TSV mapping system for getting the parameters of TSV blocks and meeting interconnection demand before 3D floorplanning. Experimental results indicate that TSV-grid can effectively improve the yield of 3D ICs with low area overhead.

用來在垂直方向連接已堆疊晶片的TSV是三維積體電路中一個重要的設計。因為只要有一根TSV損壞，就會造成整個晶片無法正常運作而被丟棄，為了提升TSV的整體良率，加入了冗餘TSV。在本篇論文中，我們為含有冗餘TSV的TSV區塊提出了一個新的結構，名為TSV-grid，這個結構特別適用於那些需要大量TSV並採用較高TSV損壞率製作技術的應用。我們也提出了一個能在三維平面規劃之前設定TSV區塊的參數並滿足TSV需求的設計流程。實驗結果顯示，這個結構確實能有效地提升三維積體電路的良率且只有些微的晶片面積增加。

[1] K. Banerjee, S. J. Souri, P. Kapur, et al., “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proceedings of the IEEE, vol. 89, no. 5, pp. 602–633, 2001.
[2] W. R. Davis, J. Wilson, S. Mick, et al., “Demystifying 3D ICs: the pros and cons of going vertical,” Proceedings of IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498–510, 2005.
[3] J. Burns, L. Mcllrath, C. Keast, et al., “Three-dimensional integrated circuits for low power, high-bandwidth systems on a chip,” Proceedings of International Solid State Circuits Conference, pp. 268-269, 2001.
[4] P. Garrou, C. Bower, and P. Ramm, “Handbook of 3D integration: technology and application of 3D integrated circuits,” published by WILEY-VCH, 2008, ISBN: 978-3-527-32034-9.
[5] H. H. S. Lee, K. Chakrabarty, “Test challenges for 3D integrated circuits,” Proceedings of IEEE Design & Test of Computers, vol. 26, no. 5, pp. 26–35, 2009.
[6] K. Y. Lee, T. C. Wang, “Post-routing redundant via insertion for yield/reliability improvement,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 303–308, 2006.
[7] U. Kang, H. J. Chung, S. Heo, et al., “8Gb 3D DDR3 DRAM using through-silicon-via technology,” Proceedings of International Solid State Circuits Conference, pp. 130–131, 2009.
[8] A. C. Hsieh, T. T. Hwang, M. T. Chang, et al., “TSV redundancy: architecture and design issues in 3D IC,” Proceedings of Deign, Automation and Test in Europe, 2010.
[9] J. Cong, J. Wei, Y. Zhang. “A thermal-driven floorplanning algorithm for 3D ICs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 306–313, 2004.
[10] J. Lu, S. Chen and T. Yoshimura, “Performance maximized interlayer via planning for 3D ICs,” Proceedings of International Conference on ASICs, pp. 1096–1099, 2007.
[11] F. Rubin, “The Lee path connection algorithm,” Proceedings of IEEE Transactions on Computers, vol. 23, no. 9, 1974.
[12] C. M. Huang, “A cost model for Chipsburger – a platform-based 3D IC design methodology,” Master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2009.
[13] C. Y. Hu, “A TSV-aware floorplanner for the Chipsburger platform-based 3D IC design methodology,” Master’s thesis, National Tsing Hua University, Hsinchu, Taiwan, 2010.
[14] GSRC benchmarks
http://www.gigascale.org/