摘要
系所別：電機工程學系　系統組
論文名稱：一個可在週期為100ns脈衝上達到1.5ps時間解析度的超寬頻脈衝雷達之時序電路
指導教授：朱大舜 博士
研究生：101061594 鄭力維

在現今我們所熟知的無線技術，不管是藍芽或 Wi-Fi 等等，主要的發展應用還是受制於頻寬，使得許多處理量大或品質高的資訊及檔案，無法快速傳輸；而超寬頻就是解決目前資訊用途短距傳輸的關鍵。
超寬頻技術在過去已有不短的發展時間，尤其是在軍事方面，可以用於雷達，偵測空中的不明飛行物體；或者用於探測地底下的不明物體，如地雷，以保障人員生命安全等等。
而超寬頻技術具有體積小、耗電低、成本低等優點，因此如果將超寬頻技術導入民生用途上想必非常適合，也會為人類的生活帶來更多的便利。
在本論文中，為了讓超寬頻脈衝雷達能擁有更好的時間解析度，提出並實現了一個使用鎖相迴路與位移寄存器結合的時序電路，使超寬頻脈衝雷達能在週期為100ns的脈衝上，達到1.5ps的時間解析度。其中包含三個鎖相迴路，一個用來確保雷達傳送端與接收端訊號的同步性，另外兩個則用於時序電路的實現。時序電路以位移寄存器為主，分成兩個部分，一部分為粗調電路，另一部分為細調電路，分成粗細調主要是防止使用太多級位移寄存器而導致電路無法運作。傳送端與接收端訊號經過位移寄存器後會產生出多個相位不同的訊號，最後再使用MUX選出我們需要的傳送端與接收端訊號做比較，計算出兩端的距離。
本論文共分五個章節，第一章為研究動機與簡介；第二章為鎖相迴路架構、及內部子電路架構與操作原理；第三章為本論文提出的時序電路架構與操作原理；第四章為軟體之模擬結果，並做討論；第五章為總結。

Abstract

Department：Electrical Engineering
Title：A Timing Circuitry of UWB Impulse Radar Achieving 1.5ps Time Resolution over 100ns
Advisor：Prof. Ta-shun Chu
Graduate student：101061594 Li-Wei Jheng

In today's wireless technology as we know, whether Bluetooth or Wi-Fi, and so on, the main

subjects of the developing application are limited to the bandwidth, making many large capacity

and high-quality information and files cannot be fast transferred. The ultra-wideband technology

is the key to solve the current application of short-range transmission of information.

Ultra-wideband technology has developed not short of time in the past, especially in the

military field. Such as radar can be used to detect UFO or unknown object underground, such as

mines, in order to protect the safety of personnel and so on. The advantage of ultra-wideband

technology is small size, low power consumption, and low cost, so if imported ultra wideband

technology into livelihood purposes is very suitable presumably, it will bring more convenience to

people's lives.

In this thesis, to make ultra-wideband impulse radar can have a better time resolution, we

proposed and implemented a timing circuitry combines phase-locked loops and shift registers,

making the ultra-wideband impulse radar can achieve 1.5ps time resolution over 100ns. It contains

three phase-locked loops, one to ensure the synchronization of the transmitter and receiver radar

signal, the other two are used to implement the timing circuitry. Timing circuitry is mainly

constituted by shift registers, it divided into two parts, one part for the coarse-tune circuit, the

other for the fine-tune circuit. We do it is to prevent to use too much shift registers which will led

to the circuit does not work. Transmitter and receiver signal after the shift register will generate

multiple signals of different phases, and finally we need to use the MUX select transmitter and

receiver signal compared to calculate the distance from both ends.

This Thesis is divided into five chapters, the first chapter is the motivation and Introduction,

the second chapter is phase-locked loop architecture, and internal sub-circuit architectures and

principles of operation, the third chapter is the timing circuitry structure and principle of operation

that we have proposed, chapter IV is the simulation results, and we’ll make some discussions, and

the fifth chapter is summary.

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