高效能靜電放電防護元件研究｜國立清華大學博碩士論文庫

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研究生：	簡鐸欣 Tuo-Hsin Chien
論文名稱：	高效能靜電放電防護元件研究 Study on the High Performance ESD Protection Device
指導教授：	徐永珍 Klaus Y. J. Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	中文
論文頁數：	68
中文關鍵詞：	靜電放電、拴鎖效應、傳輸線脈衝、閘極可控制高壓矽控整流器、系統級靜電放電測試
外文關鍵詞：	Electrostatic Discharge, Electrostatic Overstress, Latch-up, TLP, TCD, GC-HVSCR, System Level Electrostatic Discharge
相關次數：	點閱：3 下載：0
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在高壓CMOS製程設計中，積體電路(ICs)內部都必須要設計靜電防護元件(ESD Device)以避免積體電路在生產過程中被靜電放電所損傷；靜電放電防護元件主要功能是提供積體電路靜電放電路徑，以避免當靜電放電發生時電流流入IC內部造成電路損壞。目前基本的靜電防護元件有電阻(Resistor)、二極體(p-n junction Diode)、金氧半導體元件(NMOS or PMOS)、場氧化層元件(Field Oxide Device)、N型閘極趨動或閘極連接元件(Gate-driven or Gate-coupled NMOS)、雙載子電晶體(BJT)以及矽控整流器元件(SCR Device)等；每種靜電防護元件有不同的元件特性，而其靜電防護能力的好壞決定可以由Power=IESD*Voperating來定義，其中以矽控整流器元件因為具有低的持有電壓(Low holding voltage)，因此在靜電防護能力具有最佳的防護效果。但是相對的因為矽控整流器的持有電壓低於積體電路操作電壓而使得積體電路在系統級靜電放電 (System Level Electrostatic Discharge)測試而引發栓鎖效應(Latch-up)，造成IC內部電路誤動作或燒毀。靜電放電防護設計及栓鎖效應防護在靜電防護元件設計上是一種權衡設計。本論文研究主要以矽控整流器作為基本靜電防護元件，並針對對於元件特性分析及崩潰電壓(Breakdown)，驟回崩潰(Snap back)控制做探討，經由一連串的元件設計條件及分析結果最後設計出-閘極可控制之高壓矽控整流器元件(Gate Controllable High-Voltage SCR Device or GCHVSCR Device)。此靜電防護元件能夠由閘極控制改變元件結構特性來因應靜電放電及栓鎖效應做不同的防護，最後經由TMA TCAD模擬軟體(Medici & Tsuprem4)模擬分析及實際使用TLP系統量測元件特性後證實GCHVSCR確實能夠同時對積體電路靜電放電及栓鎖效應達到最佳防護效果。

目錄

摘要---------------------------------------------------------------------------------------------------Ⅰ
致謝---------------------------------------------------------------------------------------------------Ⅱ
目錄---------------------------------------------------------------------------------------------------Ⅲ
附圖索引---------------------------------------------------------------------------------------------Ⅴ
附表索引---------------------------------------------------------------------------------------------Ⅸ

第一章    序論
1    靜電放電防護背景----------------------------------------------------------------------1
2    論文概述----------------------------------------------------------------------------------2

第二章    靜電放電測試方法
1    前言----------------------------------------------------------------------------------------4
2    人體靜電放電模式(HBM)-------------------------------------------------------------4
3    機械靜電放電模式(MM)---------------------------------------------------------------6
4    元件充電靜電放電模式(CDM)-------------------------------------------------------8
5    傳輸線脈波模式(TLP Method)------------------------------------------------------10
6    系統級靜電放電模式(System Level Electrostatic Discharge Method)--------13

第三章    靜電放電測試組合
1    前言---------------------------------------------------------------------------------------15
2    ESD的測試方式及判定標準---------------------------------------------------------15
3    I/O對VDD或VSS測試---------------------------------------------------------------16
4    I/O對I/O測試---------------------------------------------------------------------------17
5    VDD對VSS測試-----------------------------------------------------------------------18
6    VDD對VSS測試(multi VDD and multi VSS ESD stress)-----------------------19
7    放大器之ESD測試--------------------------------------------------------------------20

第四章    矽控整流器在靜電放電防護電路之物理特性及操作
1    前言---------------------------------------------------------------------------------------21
2    SCR操作原理---------------------------------------------------------------------------21
3    SCR在ESD防護元件及Latch-up免疫之設計------------------------------------23
3.1    可調整持有電壓之新穎疊接閘極可控制低壓SCR(Novel Cascode
      NCLSCR Design with Tunable Holding Voltage)----------------------------23
3.2    高電流低壓觸發SCR元件(High-Current Low-Voltage Triggered SCR
      Device，HINTSCR)---------------------------------------------------------------26
3.3    閘極成對SCR(Gate-Coupled SCR)-------------------------------------------29
3.4    動態持有電壓SCR(SCR Device With Dynamic Holding Voltage, DHVSCR)-------------------------------------------------------------------------31
3.5    不同SCR設計比較--------------------------------------------------------------33
4    討論---------------------------------------------------------------------------------------34


第五章    實驗設計流程
1    前言---------------------------------------------------------------------------------------35
2    ESD防護元件設計流程比較---------------------------------------------------------35
3    ESD防護元件晶片製程流程---------------------------------------------------------36
4    ESD防護元件結構分項條件設計---------------------------------------------------42
5    SCR ESD防護元件光罩佈局設計--------------------------------------------------43
6    晶圓級TLP量測架構------------------------------------------------------------------45
7    討論---------------------------------------------------------------------------------------47

第六章    模擬及量測實驗結果分析
1    前言---------------------------------------------------------------------------------------48
2    TW-HVSCR︰光罩佈局設計條件”a ”---------------------------------------------48
3    TW-HVSCR︰光罩佈局設計條件” b ”--------------------------------------------51
4    TW-HVSCR︰光罩佈局設計條件” c ”---------------------------------------------53
5    SW-HVSCR︰光罩佈局設計條件” c ”---------------------------------------------54
6    單井高壓PNP BJT結構(SW-HV BJT_pnp)︰光罩佈局設計條件” a ”-----------------------------------------------------------------------------------------56
7    SW-HVSCR︰光罩佈局設計條件” a ”---------------------------------------------59
8    討論---------------------------------------------------------------------------------------60

第七章    新穎閘極控制式高壓矽控整流器設計
1    前言---------------------------------------------------------------------------------------61
2    GC-HVSCR元件操作特性-----------------------------------------------------------61
3    討論---------------------------------------------------------------------------------------65

第八章    總結與討論
1    總結與討論------------------------------------------------------------------------------66

參考文獻---------------------------------------------------------------------------------------------67

                                

參考文獻

[1] A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits,” 2nd Edition, John Wiley & Sons, 2002.

[2] 柯明道、許勝福, “系統層級靜電放電測試所引發之暫態觸發拴鎖效應,” 第二屆台灣靜電放電防護技術研討會

[3] Ming-Dou Ker and Sheng-Fu Hsu, “Transient-Induced Latchup in CMOS Technology:Physical Mechanism and Device Simulation,” in IEDM Tech. Dig., 2004, pp. 937-940

[4] Ming-Dou Ker and Sheng-Fu Hsu, “Physical Mechanism and Device Simulation on Transient-Induced Latchup in CMOS ICs Under System-Level ESD Tesd,” IEEE Trans. Electron Devices, vol. 52, no. 8, August. 2005

[5] ESD Association Standard Practice, “ANSI/ESD SP5.4-2004: Transient Latch-up Testing–Component Level Supply Transient Stimulation,” ESD Association, 2004.

[6] Kuo-Chun Hsu and Ming-Dou Ker, “Silicon-Controlled Recitifier with Substrate-Triggered Technoque for On-Chip ESD Protection In CMOS integrated Circuit,” A Dissertation Submitted to Institute of Electronics College of Electrical Engineering And Computer Science NCTU For the Degree of Doctor of Philosophy in Electronic Engineering, Sept, 2003

[7] 林昆賢、柯明道, “避免高壓積體電路發生拴鎖效應或類似拴鎖效應之電源間靜電放電防護設計,” 第二屆台灣靜電放電防護技術研討會

[8] Ming-Dou Ker and Hun-Hsien Chang, “Novel Cascode NCLSCR/PCLSCR Design with Tunable Holding Vlotage for Safe Whole-Chip ESD Protection,” IEEE, 1998

[9] Ming-Dou Ker, “ESD Protection for CMOS ASIC In Noisy Environments with High-Current Low-Voltage Triggering SCR Devices,” IEEE, 1997

[10] Chen-Shang Lai, Meng-Hwang Liu, Shiu Su, and Tao-Cheng Lu, “A Novel SCR ESD Protection structure with Low-Loading and Latchup Immunity for High-Speed I/O Pad,” IEEE, 2003

[11] Chun-Hsiang Lai, Meng-Hwang Liu, Shiu Su, Tao-Cheng Lu, and Sam pan, “A Novel Gate-Coupled SCR ESD Protection Structure With High Latchup Immunity for High-Speed I/O Pad,” IEEE EDL, vol. 25, NO. 5, May, 2004

[12] Ming-Dou Ker and Zi-Ping Chen, “SCR Device With Dynamic Holding Voltage for On-Chip ESD Protection in a 0.25-um Fully Salicided CMOS Process,” IEEE Trans on Electron Device, vol. 51, NO. 10, OCTOBER 2004

[13] Ming-Dou ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE, “The Impact of low-Holding-Voltage Issue in High-Voltage CMOS Technology and the Design of Latchup-Free Power-Rail ESD Clamp Circuit for LCD Driver ICs,” IEEE Journal of Solid-State Circuit, vol. 40, NO. 8, August, 2005

[14] Akram A. Salman, Member, IEEE, Robert Gauthier, Chris Putnam, Philipp Riess, Mujahid Muhammad, Min Woo, and Dimitris E. Ioannou, Member, IEEE, “ESD-Induced Oxide Breakdown on Self-Protecting GG-nMOSFET in 0.1-um CMOS Technology,” IEEE Transactions on device and materials reliability, vol. 3, NO. 3, Sept, 2003

[15] Ming-Dou Ker, Senior Member, IEEE, and Hun-Hsien Lin, Student Member, IEEE, “Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design,” IEEE EDL, vol. 25 NO.9, Sept, 2004

[16] Ming-Dou Ker, Senior Member, IEEE, and Kuo-Chun Hsu, Member, IEEE, “Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effective ESD Protection in a 0.13-um CMOS Process,” IEEE Transactions on device and materials reliability, vol. 5, NO. 3, Sept, 2005

[17] D. Tremouilles, G. Bertrand, M. Bafleur, F. Beaudoin, P. Perdu, L. Lescouzeres, “TCAD and SPICE Modeling Help Solve ESD Protection Issues in Analog CMOS Technology,” Proc. 23rd international conference on microelectronics (MIEL 2002), vol. 2, nis, Yugoslavia, 12-15, May, 2002

[18] A. Concannon, V. A. Vashchenko, M. ter Beek, and P. Hopper, “A DEVICE LEVEL
NEGATIVE FEEDBACK IN THE EMITTER LINE OF SCR-STRUCTURES AS A METHOD TO REALIZE LATCH-UP FREE ESD PROTECTION,” IEEE 41st Annual international reliability physics symposium, Dallas, Texas, 2003

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