在本篇論文，我們設計一個以精簡指令集電腦架構為基礎(RISC-based)的數位訊號處理核心(DSP Core)。設計重點在於提供高運算能力和提升程式碼密度。為了提供高運算能力，我們的設計可以在同一時脈執行兩個指令，並且包含最多八個運算元。另外一方面，我們設計一套高程式碼密度的指令集，同時我們將高度相關的數個指令結合和為單一指令，以此來提升程式碼密度。
由於通訊、多媒體領域所需的資料計算量越來越龐大，所需的數位訊號處理器必須擁有更高的工作時脈以及高度平行化的執行能力以提供更高的運算能力，所以進來的設計多朝向精簡指令集電腦架構的方向設計，新的架構的確較容易提升工作頻率和平行化執行能力。可是另一方面，新的架構卻大大的降低了程式碼密度，而較高的程式碼密度對於嵌入式系統卻是必要的需求，因為嵌入式系統中的記憶體大小通常都是受限的，較佳高程式碼密度代表著較大的應用程式可以被載入於大小固定的嵌入式記憶體中。

基於高計算能力和高程式碼密度的需求，我們以精簡指令集電腦架構為基礎我們的新架構和高密度的指令集，並且利用可合成的硬體電路描述語言將這個數位訊號處理器架構和指令集實際設計出來。接下來的章節重點為下：第一章我們簡介數位訊號處理器中常使用的技術和我們的設計重點；第二章快速的瀏覽我們的架構；第三章介紹設計中的管線處理技巧；第四章介紹運算單元的電路設計；第五章簡介記憶體架構和自動位址產生器；第六章介紹所設計的複合指令集；最後第七章是實驗結果和第八章的結論。

We design a RISC-based DSP core. We focus on performance and code density. We use VLIW and SIMD techniques in our design to provide higher computation power. Moreover, we combine some instructions into a compound instruction to improve code density. We have implemented the DSP core in synthesizable RTL Verilog. The core is able to run at 120 MHz when targeted towards a TSMC 0.35 um cell library.

[1] Michael Dolle, Satwinder Jhand, Walter Lehner, Otto Muller, Manfred Schlett, "A 32-b RISC/DSP Microprocessor with Reduced Complexity", IEEE JOURNAL of Solid-State Circuits, VOL. 32, pp. 1095-1066, JULY 1997.
[2] Manfred Schlett, "The Risc Challenge In Signal Processing", Proc. of ICECS'96, pp. 550-530, 1996.
[3] Michael R. Smith, "How RISCy is DSP?", Proc. of IEEE Micro, pp. Vol. 12, pp.10-23, Dec. 1992.
[4] Acken K.P., Irwin M.J., Owens R.M, "Power comparisons for barrel shifters", Proc. of Int. Symp. on Low Power Electronics and Design, pp. 209-212, 1996.
[5] Farooqui A.A., Oklobdzija V.G., "General data-path organization of a MAC unit for VLSI implementation of DSP processors", Prof. of Int. Symp. on Circuits and Systems, pp. 260-263.
[6] Alidina M., Burns G., Holmqvist C., Morgan E., Rhodes D., Simanapalli S., Thierbach M., "DSP16000:a high performance, low-power dual-MAC DSP core for communications applications", Proc. of Custom Integrated Circuits Conference, pp. 119-122.
[7] "TMS320C54xDSP Reference Set Volume 1 CPU and Peripherals", Texas Instruments, 1999
[8] "TMS320C60 CPU and Instruction Set Reference Guide", Texas Instruments, 1999
[9] "TigerSharc DSP Hardware Specification", Analog Device, 1999
[10] "TigerSHARC Instructon Set", Analog Device, 1999
[11] "ADSP-2106x SHARC User's Manu", Analog Device, 1996
[12] "ADSP-2100 Family User's Manual Third Edition", Analog Device, 1995
[13] "The SPARC Architecture Manual Version 8", SPARC International , 1991
[14] "Application Specific Microprocessor Solutions: Data sheet for XTENSA V1", Tensilica, 1999
[15] "The IDT79R3071, IDT79R3081 RISCController Hardware Users's Manual",Integrated Device Technology, 1994
[16] Phil Lapsley, Jeff Bier, Amit Shoham, Edward A. Lee, "DSP Processor Fundamentals", IEEE Press, 1997
[17] Lars Wanhammar, "DSP Integrated Circuits", Academic Press, 1999
[18] David A. Patterson, John L. Hennessy, "Computer Organization & Design: The Hardware/Software Interface", Morgan Kaufmann Publishers, 1997
[19] David A. Patterson, John L. Hennessy, "Computer Architecture & Quantitative Approach, Morgan Kaufmann Publishers, 1990
[20] "Snopsys Design Compiler Reference Manual: Constraints and Timing v1998.02", Synopsys, 1998
[21] "Snopsys Design Compiler Reference Manual: Optimization and Timing Analysis v1998.02", Synopsys, 1998