研究生: |
歐俊庭 Ou, Chun-Ting |
---|---|
論文名稱: |
以鎢為主高功函數金屬閘極之金氧半元件製程研究 Process Study for MOS Devices with Tungsten Based High Work Function Metal Gates |
指導教授: |
張廖貴術
Chang-Liao, Kuei-Shu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2011 |
畢業學年度: | 99 |
語文別: | 中文 |
論文頁數: | 95 |
中文關鍵詞: | 鎢 、高功函數 |
相關次數: | 點閱:3 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
為了改善MOSFET電晶體的性能,元件的尺寸被要求越來越小,許多新穎的研究成果已被發表出來,其中,高功函數金屬閘極的研究相當引人注目。
本論文研究的重點放在高功函數金屬閘極和cap layer 金屬的材料選擇上。第一部份為研究WHfxN(WHf_H)和TiN/WHfxN(TWHf_H),運用在high-k介電層材料 HfAlO。根據學長的研究結果,單層WHf_H的電特性極佳。沉積cap layer TiN主要的想法是,它能阻擋外界的氧原子進入而向下擴散,並保留單層WHf_H的電特性。由實驗結果發現,TWHf_H 因為有cap layer TiN的作用,在經過高溫退火之後,雖然抑制了氧原子的擴散,使得EOT和Jg的熱穩定性較好。但在可靠性上的表現則較差。功函數方面,兩種結構功函數在PMA900oC下仍有5.02 eV以上,相當適合於pMOS元件的應用。
第二部分為探討堆疊金屬閘極TiN/WN (TW_H)和TiN/WHfxN(TWHf_H ),並運用在high-k介電層材料 HfAlO。摻雜Hf主要的想法是,期望能改善金屬閘極和閘介電層之間的介面品質。由實驗結果發現,TWHf_H在經過高溫退火之後,在多項電特性都獲得改善。在功函數的熱穩定性上,摻雜Hf使得結晶更完美,功函數也較好,適合於pMOS元件的應用。
第三部分探討堆疊金屬閘極TiN/WN(TW_H)和TaTixN/WN(TaTiW_H),並運用在high-k介電層材料 HfAlO。延續第一部分,由於TW_H在經過高溫退火之後,Ti擴散較為嚴重,所以在TiN摻雜Ta,期望能抑制Ti擴散。由實驗結果發現,TaTiW_H閘極在經過高溫退火之後,氧原子和金屬離子的擴散並不明顯,故其熱穩定性和可靠度都獲得改善。功函數方面,TaTiW_H 高功函數結晶更明顯,功函數較大,適合於pMOS元件的應用。
參考文獻
[1] M. S. Krishinan, et al., IEDM, p. 571, 1998
[2] C. Hobbs, et al., IEEE Symp. On VLSI Technology Tech. Dig., 2-1. 2003.
[3] C. Hobbs, et al., IEEE Elec. Dev. Lett., vol.51(6), pp.978, 2004.
[4] Seiichiro KAWAMURA, IEEE Custom Integrated Circuits Conference, p.467-474, 2002.
[5] D. G. Park, et al., IEDM Tech. Dig., p.671, 2001.
[6] H. Zhong, et al., Appl. Phys. Lett., vol.78, p.1134-1136, 2001.
[7] H. Zhong, et al., J. of Electronic Materials, vol.30, p.1493, 2001.
[8] Y. H. Kim, et al., IEDM Tech. Dig., p.667, 2001.
[9] J. K. Schaeffer, et al., MRS spring meeting, April, 2002.
[10] I. Polishchuk, et al., IEEE Electron Device Lett., vol.22, p.444, 2001.
[11] H. Zhong, et al., IEDM Tech. Dig., p.467, 2001.
[12] C. Wang, et al., Appl. Phys. Lett., vol.83 (2), pp.308, 2003.
[13] C. Hobbs, et al., Symp. VLSI Tech. Dig., pp.9, 2003
[14] IEDM Short Course 2004, Mark Rodder, Texas Instrument.
[15] IEDM Short Course 2004, Stefan De Gendt, IMEC.
[16] W. Zhu, et al., Trans. Elec. Dev. Lett., vol.51 (1), pp.98, 2004.
[17] M. V. Fischetti, et al., J. Appl. Phys., vol.90 (9), pp.4587, 2001.
[18] Robert Chau, et al., Elec. Dev. Lett., vol.25 (6), pp.408, 2004.
[19] H. Ono, et al., Appl. Phys. Lett., vol.73, no.11, p.1517, 1998.
[20] R. Beyers, J. of Appl. Phys., vol.56, p.1, 1984.
[21] V. Misra, et al., 2002, MRS bulletin, vol.27, no.3, p.212
[22] C.Wang,et al.,Appl.Phys.Lett.,vol.83,pp.308,2003
[23] S. Zafar et al., Apply Phys. Letter, vol. 80, pp. 4858-4860, 2002.
[24] Huang-Chun Wen et al., July 2006, IEEE EDL, vol.27, no.7 pp.598-601
[25] Po-Yen. Chien, Integration of electrical characteristics for MOS devices with Molybdenum metal gate 2007, thesis in the Department of Engineering and System Science, NTHU.
[26] N. V. Nguyen, et al., Appl. Phys. Lett., 77, 3012 (2000).
[27] P. T. Gao, et al., Thin Solid Films, 377, 557 (2000).
[28] K. Kukli, et al., Thin Solid Films, 260, 135 (1995).
[29] M. Cassir, et al., Appl. Surf. Sci., 193, 120 (2002).
[30] C. M. Perkins, et al., Appl. Phys. Lett., 78, 2357 (2001).
[31] C. Chaneliere, et al., Microelectron. Reliab., 39, 261 (1999).
[32] D. D. L. Chung, et al., X-Ray Diffraction at Elevated Temperatures: A Method for In-Situ Process Analysis, Chap.1, VCH Publishers, New York (1993).
[33] Powder Diffraction File: Inorganic and Organic Data Book, PDF#19-1299, 25-0922, 25-1257, 25-1366, 27-1402, 34-1084, 42-0060, 42-1120, and 72-1088, JCPDS – International Center for Diffraction Data, American Society for Testing and Materials, Swarthmore, PA (1950-2003).
[34 ] K. Onishi, et al., Symp. VLSI Tech., p.131, 2001.
[35] Po-Yen. Chien, Integration of electrical characteristics for MOS devices with Molybdenum metal gate 2007, thesis in the Department of Engineering and System Science, NTHU.
[36] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed., John Wiley & Sons, New York (1998).
[37] Chih-Feng HUANG, Japanese Journal of Applied Physics Vol. 47, No. 2, 2008, pp. 872–878
[38] Integration of Metal Gate and High-k Gate Dielectric for Advanced MOS Devices H. C. Chang .2006
[39] Stanley Wolf, Silicon Processing for VLSI ERA, vol.2, 1990
[40] J. F. Kang, et al., IEEE Electron Device Lett., 2005; 26: 237-9.
[41] Heiji Watanabe, et al., APL 85, p.449, 2004
[42] Jahan C, et al., Microelectron Reliab. 37 1529-32, 1997.
[43] Paul E. Nicollian, et al., in IRPS, p.400-404, 1999
[44] Huei-Chi Chuang, “Electrical characteristic enhancement of MOS device with gate stack dielectrics and interfacial layer engineering ”2007, thesis in the Department of Engineering and System Science, NTHU.
[45] Yasushi AKASAKA et al., Japanese Journal of Applied Physics Vol. 45, No. 4B, 2006, pp. 2933–2938.
[46] Jaehyun Kim and Kijung Yung, ECS, 152 (10) F153-155, 2005
[47] V. Mikhelashvili, e al., IEEE EDL 27, p.344, 2006
[48] Chin-Lung Cheng,et al., Device and Materials Reliability, IEEE Transactions on, vol.10, p.116-122, 2010