隨著製程的進步、單位元件尺寸的縮小，邏輯閘延遲的缺陷更顯嚴重。為了確保電路上的時序要求，即時性測試被廣泛應用在測試電路的效能。然而，在即時性測試的當下，可能導致數量可觀的元件同時發生轉換，使得晶片內部的供電不穩定，產生所謂的電流電阻壓降效應。這會電路功能發生錯誤，並誤判電路本身為錯誤。故我們需要設法降低在即時性測試中的元件轉換率。
X 填值的方法最常被人用來解決即時性測試的電流電阻壓降效應，X 值的比例和特性則支配X 填值的方法的效能。然而目前為止，還未有一個專門針對特定區域增加X 值的演算法，以達到減低單位區塊內元件同時發生的轉換。
在這篇論文中，我們改變以往晶片測試中，增加測試樣本X 分佈的方法–平均分佈或最大X 數量，我們提出一個針對特定壓降區域增加X 值的方法；加入考慮電路裡各元件的實際位置後，我們針對實際影響該區域的測試位元作測試舒緩，達到減少測試時發生的大量元件轉換，進而解決測試時產生的壓降效應。

To guarantee an application specific integrated circuits (ASIC) meets the timing requirement, at-speed scan testing becomes an indispensable procedure to verify the erformance of ASIC. However, at-speed scan test suffers from the test-induced yield loss. Because, the switching activity in testing is often higher than that in normal function. The switching-induced large current withdrawing in turn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. Nevertheless, none of the existing test relaxation schemes taking the physical location of X-bits into account. Hence it is adversely affecting the effectiveness of reducing switching activities of IR-drop hot zone. In this thesis, we propose a novel test relaxation approach - Physical-Location-Aware X-Identification, which consider the physical information of sensitized scan cells induced switching activities. The experiment results on ITC'99 shows that we have average 42.70% potential transition reduction for the IR-drop hot zone.

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