嵌入式時間參數量測｜國立清華大學博碩士論文庫

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研究生：	蕭鳴均 Ming-Jun Hsiao
論文名稱：	嵌入式時間參數量測 Built-in Timing Parametric Measurement
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	72
中文關鍵詞：	時間參數量測、雙斜率轉換、雙指數曲線轉換、設定時間、保持時間、時間數位轉換器、安定時間補償
外文關鍵詞：	timing measurement, dual-slope, dual exponential curve, setup time, hold time, time-to-digital converter (TDC), settling time canceling
相關次數：	點閱：4 下載：0
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隨著深次微米製程的進步以及降低成本的需求，將各式各樣的線路整合至一個系統晶片已經是一種趨勢。但是由於高度整合的結果，使得各個線路缺乏足夠的可控制性與可觀測性，也造成了需要額外的測試存取機制以及高速的自動測試機台來完成測試，因此造成了測試成本的增加。除此之外，額外的測試存取機構也帶來額外的時間延遲而造成測式時間參數上的困難以及準確度。而嵌入式的量測可以在晶片內完成準確的量測，同時又能與低價的自動測試機台合作來得到量測數據，因而能降低測試成本。
根據時間放大的觀念，在本論文中提出了兩種時間量測線路。第一種是根據傳統的雙斜率轉換並同時考量安定時間等非理想因素而將可測範圍向下延伸至0.5奈秒。我們所提出的是一種自動時序的方法，也因此不需要額外的控制線路，所以在0.25微米的CMOS製程下的面積只有72微米乘以43微米，同時我們的線路也能夠量測設定時間與保持時間。第二種則是依據一個稱為雙指數曲線轉換的全新方法。由於採用的是最自然的指數曲線，所以我們的線路可以不需要高線性度的元件，因而降低了設計上的難度。更重要的是，雙指數曲線轉換的方法不需要參考的時間單位來作為校正輸入，因此可以避免參考時間的不確定性如時基抖動所造成的誤差。同時我們也根據誤差分析提出了一個設計指南。

As the progress in deep sub-micron technology, the integration of more heterogeneous components into a System-On-a-Chip is performed for reducing production cost. However, the testing cost is increased rapidly due to lack of controllability and observability, and thus general test access mechanism and high-performance Automatic Test Equipments (ATEs) are needed to overcome the testing problems. Furthermore, the required general test access mechanism usually introduces extra timing penalties for parametric testing, and hence reduces the accuracy of AC measurement. In this way, embedded measurements are needed to accurately measure the parameters inside the chip with the cooperation of low-cost ATEs for reducing test cost.
Based on the pulse-stretching principle, two types of timing measurement circuits are proposed in this thesis for embedded measurement. The first one is founded on traditional dual-slope conversion while considering the non-ideal effects such as settling time to extend the measurable range below 0.5ns. Since a self-timed method is proposed to reduce the requirements of controller, the area is only 72mm X 43mm n a 0.25mm 1P5M CMOS technology, and the capability of setup/hold time measurement is provided in the meanwhile. The second one is a brand-new method based on dual-exponential curve transformation. By utilizing the inherent exponential curves, high-linearity components are not necessarily required and the design efforts are relaxed. Furthermore, the dual-exponential curve transformation needs no reference time intervals for calibration, and hence it immunes to the uncertainties such as jitter of the reference inputs. A design guideline is also proposed for this method based on the error analysis.

Contents
Chapter 1.    Introduction    1
Chapter 2.    Overview    4
1.    Built-in timing measurement for embedded memories    4
2.    Issues of timing parametric measurement    6
3.    Principle of Vernier delay line    11
4.    Principle of Vernier oscillator    12
5.    Principle of dual-slope conversion for time interval measurement    13
Chapter 3.    The Dual-Slope Method    16
1.    The proposed method: version 1    16
1.1.    Ratioed resistor array    17
1.2.    Comparator (CMP)    17
1.3.    Control logic    20
1.4.    Offset Canceling (AutoZero)    21
2.    The proposed method: version 2    23
2.1.    The block diagram of the proposed circuit    24
2.2.    The self-timed method    25
2.3.    Settling time cancellation    26
3.    Linearity analysis and calibration    28
3.1.    Linearity analysis    28
3.2.    Calibration    30
4.    Simulations and experimental results    34
4.1.    Access time measurement    35
4.2.    Setup/hold time measurement    37
4.3.    Experimental results    38
5.    Comparisons and discussions    40
6.    A complete access time measurement unit for embedded memory    42
6.1.    TVC and VTC    44
6.2.    The implementation of proposed TDC    45
6.3.    The peak detector and comparator    46
6.4.    The measurement flow    49
6.5.    Experimental results    50
7.    Summary    53
Chapter 4.    Dual-Exponential Curve Transformation    54
1.    The Basic Principle    54
2.    The Calibration Methodology    56
3.    The Implementation    56
3.1.    The Operation Principle    57
3.2.    The Calibration Process    60
4.    Error Analysis    61
4.1.    Quantization error of calibration    61
4.2.    Parasitic Effect    62
5.    Simulation Results    63
6.    Summary    67
Chapter 5.    Conclusions and Future Works    68
References    70

                                

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