使用三重模組冗餘之投票前的同步技術之容錯型鎖相迴路電路設計

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研究生：	楊舜華 Yang, Shun-Hua
論文名稱：	使用三重模組冗餘之投票前的同步技術之容錯型鎖相迴路電路設計 Fault and Soft-Error Tolerant Phase-Locked Loop Using a Synchronization-before-Voting TMR Scheme
指導教授：	黃錫瑜 Huang, Shi-Yu
口試委員:	呂學坤 Lu, Shyue-Kung 温宏斌 Wen, Hung-Pin 黃宗柱 Huang, Tsung-Chu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	48
中文關鍵詞：	鎖相迴路、三重模組冗餘、錯誤容忍、鎖延遲迴路、投票前的同步技術、軟性錯誤
外文關鍵詞：	PLL, TMR, fault tolerant, DLL, synchronization before voting, soft error
相關次數：	點閱：3 下載：0
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在產生高頻信號的IC中鎖相迴路是必不可少的。對於安全關鍵的應用，容錯(Fault and Soft-Error Tolerance)方法是我們一直追求的特性。但是要如何使鎖相迴路有容忍錯誤的能力還是一項挑戰。在本論文中，我們提出一個使用三重模塊冗餘(Triple Module Redundancy)技術之容錯型鎖相迴路電路設計去應對這個問題。在本論文中，模擬的結果顯示單純的使用三重模塊冗餘技術之鎖相迴路無法正常運作，除非我們能解決訊號同步的問題，因此我們提出一個在三重模塊冗餘投票前的同步技術完成草率的容錯型鎖相迴路電路設計。除此之外，我們藉由細心擺放相位比較器並改用感官放大器(Sense Amplifier)來優化電路表現及減少面積。通過細心擺放，訊號抖動量的峰值差可以由使用草率容錯型鎖相迴路電路的25皮秒降到12皮秒，而通過使用感官放大器取代原本的相位比較器，相比原始的鎖相迴路電路的面積倍率能從687%縮減到675%
我們獨特的貢獻是使用”投票前同步技術”來達到容錯能力同時也維持訊號抖動量的穩定。最後我們使用90nmCMOS製程的後端模擬來展示我們的鎖相迴路可以容忍來自在線的錯誤還有來自外部高能輻射帶來的軟錯誤並且不會有可觀的抖動性能損失。

A Phase-Locked Loop (PLL) circuit is indispensable in producing high-speed on-chip clock signals in an IC. For safety-critical applications, fault and soft-error tolerance is often a desirable feature. However, how to achieve that goal for a PLL circuit remains a challenge. In this paper, we address this challenge with a TMR-based FET PLL design. In this thesis, we first show that a naïve FET-PLL using the Triple-Module Redundancy (TMR) technique cannot work unless the input of the voter is synchronized, by using a Synchronization-before-Voting TMR Scheme, the careless FET-PLL can tolerant fault and soft error. Furthermore, we enhance it with careful Phase Detector placement and using a Sense Amplifier to optimize the performance and area overhead. Through careful placement, the peak-to-peak jitter over 1000 clock cycles in PLL can be reduced from 25ps using the careless FET-PLL to 12ps, and by using Sense Amplifier the Area Overhead compared to primitive PLL can be reduced from 687% to 675%
Our unique contribution is a “synchronization-before-voting” scheme so that the fault and soft-error tolerance and the jitter performance can be maintained at the same time. Post-layout simulation using a 90nm CMOS process demonstrates that our PLL can indeed withstand the attack of online faults as well as soft errors without suffering from significant jitter performance loss.

Abstract    ii
摘要    iii
誌謝辭    iv
Content    v
List of Figures    vii
List of Tables    ix
Chapter 1 Introduction    1
1.1 Introduction    1
1.2 Thesis Organization    4
Chapter 2 Preliminaries    5
Chapter 3 Proposed Fault and Soft-Error Tolerance Scheme for PLL    9
3.1 Predicament of Naïve TMR-based PLL    9
3.2 FET-PLL using a Synchronization-before-Voting TMR Scheme    11
3.2.1 Architecture of FET-PLL    11
3.2.2 Operation of FET-PLL    13
3.2.3 Detail component of FET-PLL    15
Chapter 4 Experimental Results of FET-DLL    29
4.1 Layout and simulation result under normal conditions    29
4.2 Jitter performance under different process corner    32
4.3 Jitter performance of Monte Carlo simulation    33
4.4 Impact of various Phase detectors    34
4.5 Simulation of Fault scenarios    37
4.5.1 Scenario 1    38
4.5.2 Scenario 2    39
4.5.3 Scenario 3    41
4.5.4 Scenario 4    42
Chapter 5 Conclusion    45
References    46


                                

[1] T. A. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, IEEE Journal of Solid-State Circuits, Vol. 28, No. 5, pp. 553–559, May 1993.
[2] D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong, “A 0.3-1.4 GHz All-Digital Fractional-N PLL With Suppressive Loop Gain Controller”, IEEE Journal of Solid-State Circuits, Vol. 45, No. 11, pp. 2300–2311, Nov. 2010.
[3] T. Olsson and P. Nilsson, “A Digitally Controlled PLL for SoC Applications,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 751–760, May 2004.
[4] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A Portable Digitally Controlled Oscillator using Novel Varactors,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 5, pp. 233–237, May 2005.
[5] H.-J. Hsu, and S.-Y. Huang, “A Low-Jitter ADPLL via a Suppressive loop filter and an Interpolation-Based Locking Scheme”, IEEE Trans. on Very Large Scale Integration Systems, Vol. 19, No. 1, pp. 165–170, Jan. 2011.
[6] C.-W. Tzeng and S.-Y. Huang, “Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration”, IEEE Trans. on VLSI Systems, Vol. 22, No. 3, pp. 621-630, Mar. 2014.
[7] A. N. Nemmani, “Design Techniques for Radiation Hardened Phase-Locked Loops,” master’s thesis, Oregon State University, A874174, August 2005.
[8] Y. Boulghassoul, L. W. Massengill, A. L. Sternberg, B. L. Bhuva, and W. T. Holman, “Towards SET Mitigation in RF digital PLLs: From Error Characterization to Radiation Hardening Considerations,” IEEE Trans. Nuclear Science, Vol. 53, No. 4, pp. 2047-2053, Aug. 2006.
[9] T. D. Loveless, L. W. Massengill, B. L. Bhuva, W. T. Holman, A. F. Witulski, and Y. Boulghassoul, “A hardened-by-design technique for RF digital phase-locked loops,” IEEE Trans. Nuclear Science, vol. 53, no. 6, pp. 3432–3438, Dec. 2006.
[10] T. D. Loveless. L. W. Massengill, B. L. Bhuva, W. T. Holman, R. A. Reed, D. McMorrow, J. S. Melinger, and P. Jenkins”, “A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS,” IEEE Trans. Nuclear Science, Vol. 54, No. 6, pp. 2012-2020, Dec. 2007.
[11] Z. Chen, M. Lin, Y. Zheng, Z. Wei, S. Huang, and S. Zou, "Single-Event Transient Characterization of a Radiation-Tolerant Charge-Pump Phase-Locked Loop Fabricated in 130 nm PD-SOI Technology", IEEE Trans. Nuclear Science, Vol. 63, No. 4, pp. 2402-2408, Aug. 2016.
[12] E. W. Richards, T. D. Loveless, J. S. Kauppila, T. D. Haeffner, W. T. Holman, and L. W. Massengill, “Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI”, IEEE Transactions on Nuclear Science, Vol. 67, No. 6, pp. 1144-1151, 2020.
[13] R. L. Shuler, C. Kouba, and P. M. O’Neill, “SEU Performance of TAG Based Flip-Flops,” IEEE Transactions on Nuclear Science, Vol. 52, No. 6, pp. 2550-2553, Dec. 2005.
[14] Dave Y.-W. Lin and Charles H.-P. Wen, "Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop,” IEEE Trans. on Computers (TC), Vol. 71, No. 5, pp. 1008-1020, 2022.
[15] T. D. Loveless, L. W. Massengill, B. L. Bhuva, W. T. Holman, M. C. Casey, and R. A. Reed, “A Probabilistic Analysis Technique Applied to a Radiation-Hardened-by-Design Voltage-Controlled Oscillator for Mixed-Signal Phase-Locked Loops,” IEEE Transactions on Nuclear Science, Vol. 55, No. 6, pp. 3447–3455, Dec. 2008.
[16] R. L. Shuler, “SEU/SET Tolerant Phase-Locked Loops”, Chapter 12 of Radiation Effects in Semiconductors edited by K. Iniewski, ImprintCRC Press, Jan. 2010.
[17] J.-Y. Yang and S.-Y. Huang, “Process Resilient Fault-Tolerant Delay Locked Loop using TMR with Dynamic Timing Correction”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 41, No. 5, pp. 1563-1572, May 2022.
[18] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.
[19] Z.-H. Zhang, W. Chu, and S.-Y. Huang, "A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop", IEEE Access, Vol. 7, pp. 97928-97937, Aug. 2019.
[20] K. Arshak, O. Abubaker, and E. Jafer, “Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed and low jitter PLL,” IEEE International Caracas Conference on Devices, Circuits and Systems, Vol. 1, Nov. 2004.

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