在三維晶片技術中，不同的晶片可經由穿矽連接孔連接，以堆曡的方式整合而成，其中有許多的穿矽連接孔是應用於晶片的電源接腳，將電源電壓傳送至各個晶片，而非應用於傳遞訊號。在已發表的文獻中，所提出的這些測試方法，還尚未深入探討關於電源電壓用穿矽連接孔的檢測技術。
在本篇論文裡，我們提出一個電源電壓用穿矽連接孔的測試架構與方法，在生產測試階段，藉由埋藏在電源電壓用穿矽連接孔的端點上，以環形震盪器為基礎的監測電路(建立在可調整的測試架構上，以因應大量的電源電壓用穿矽連接孔)，監測是否有過多的電源電壓落差。我們所提出方法的特色之一，採用[15]所發表的量測技術，可以監測動態的峰值電源電壓落差(藉由支援高取樣率的監測電路，比如1 GHz)，有別於先前同樣以環形震盪器為基礎監測電路的方法，只是監測一段長時間的平均電源電壓落差。為了提高測試結果的精準度，量測與資料分析，都應考量每個監測電路的製程變異，我們所提出方法的另一項關鍵特色，在資料分析的階段，先進行監測電路的製程變異校正，再分析資料的監測結果。檢測出這些發生在電源電壓傳遞網路上的微小缺陷是必要的，假使這些缺陷未被檢測出來，系統在運作的過程中，便可能因過多的電源電壓落差，發生一個短暫的時序故障。

Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this work, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (with a high sampling rate monitor, e.g., 1GHz), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.

[1] S. L. Wright, et al, "Characterization of Micro-bump C4 Interconnects for Si-Carrier SOP Applications," Proc. of Electronic Components and Technology Conf., pp. 633-640, 2006.
[2] B. Banijamali, S. Ramalingam, K Nagarajan, and R. Chaware, “Advanced Reliability Study of TSV Interposers and Interconnects for the 28nm Technology FPGA,” Proc. of IEEE Electronic Components and Technology Conf., pp. 285–290, 2011.
[3] S. L. Wright, et al, "Micro-interconnection Reliability: Thermal, Electrical and Mechanical Stress", Proc. Electronic Components and Technology Conf., pp. 1278-1286, May 2012.
[4] Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[5] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation”, Proc. of Design Automation Conf., pp. 10240-1030, June 2012.
[6] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[7] S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 8, pp. 1258-1268, Aug. 2014.
[8] A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, “On-Die Droop Detector for Analog Sensing of Power Supply Noise,” IEEE J. of Solid-State Circuits, vol. 39, no. 4, pp. 651-660, April. 2004.
[9] R. Petersen, P. Pant, P. Lopez, A. Barton, J. Ignowski, and D. Josephson, “Voltage Transient Detection and Induction for Debug and Test,” Proc. of IEEE Int’l Test Conf., pp. 1-10, Nov. 2009.
[10] U. Kang, H. Chung, S. Heo, D. Park, H. Lee, J. Kim, S. Ahn, S. Cha, J. Ahn, D. Kwon, et al., “8 GB 3-D DDR3DRAM using Through-Silicon-Via Technology,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 1, pp. 111–119, 2010.
[11] Z. Abuhamdeh, P. Pears, J. Remmers, A. L. Crouch, and B. Hannagan, “Characterize Predicted vs. Actual IR Drop in a Chip Using Scan Clocks”, IEEE Proc. of Int’l Test Conference (ITC), PP. 1-8, Oct. 2006.
[12] Z. Abuhamdeh, V. D'Alassandro, R. Pico, D. Montrone, A. Crouch, and A. Tracy, “Separating Temperature Effects from Ring-Oscillator Readings to Measure True IR-Drop On a Chip”, IEEE Proc. of Int’l Test Conference (ITC), pp. 1-10, Oct. 2007.
[13] Y. Miyake, Y. Sato, S. Kajihara, and Y. Miura, “Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test,” Proc. Of Asian Test Symp., pp. 156 - 161, Nov. 2014.
[14] A. Sehgal, Peilin Song, and Keith A. Jenkins, “On-Chip Real-Time Power Supply Noise Detector,” Proc. of IEEE European Solid-State Circuits Conf., pp. 380-383, Sept. 2006.
[15] C.-H. Hsu, S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, "Worst-Case IR-Drop Monitoring with 1GHz Sampling Rate," Proc. of VLSI Design, Automation, and Test (VLSI-DAT), (April 2013).
[16] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, March 2014.
[17] Y. Ogasahara, M. Hashimoto,and T. Onoye, “All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform,” IEEE J.Solid-State Circuits, vol.44, no.6, pp. 1745-1755, Jun. 2009.
[18] S.-W. Chen, M.-H. Chang, W.-C. Hsieh, and Wei Hwang, “Fully On-Chip Temperature, Process, and Voltage Sensors,” Proc. of IEEE Int’l Symp. on Circuits and Systems, pp. 897-900, Jun. 2010.
[19] Dietel, S., Hoppner, S., Brauninger, T., Fiedler, U., Eisenreich, H., Ellguth, G., Hanzsche, S., Henker, S., Schüffny, R., “A compact on-chip IR-drop measurement system in 28 nm CMOS technology,” Circuits and Systems (ISCAS), 2014 IEEE International Symposium, pp. 1219-1222, Jun. 2014.
[20] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.