應用於深度神經網絡資料處理以基於區域計算單元6T靜態隨機存取記憶體之記憶體內運算巨集

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研究生：	涂詠甯 Tu, Yung-Ning
論文名稱：	應用於深度神經網絡資料處理以基於區域計算單元6T靜態隨機存取記憶體之記憶體內運算巨集 A Local Computing Cell Based 6T SRAM Computing-in-Memory Macro for Deep Neural Network Data Processing
指導教授：	張孟凡 Chang, Meng-Fan
口試委員:	呂仁碩 Liu, Ren-Shuo 邱瀝毅 Chiou, Lih-Yih
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2019
畢業學年度：	108
語文別：	英文
論文頁數：	55
中文關鍵詞：	靜態隨機存取記憶體、記憶體內運算、人工智慧、卷積神經網絡
外文關鍵詞：	SRAM, CIM, AI, CNN
相關次數：	點閱：3 下載：0
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近年來，深度神經網絡的快速發展和各種邊緣設備的廣泛使用大大增加了數據傳輸量。然而，數據在中央處理器和記憶體之間移動的過程消耗了傳統馮紐曼架構中的大部分能量，我們將其稱為馮紐曼瓶頸。因此，記憶體內運算已經成為解決這一瓶頸的發展目標。
記憶體內運算計算可以同時具有運算和存儲功能。在讀取數據之前就完成計算，並可以直接傳輸結果，以減少移動大量的數據。為了達到上述目的，本研究的設計概念是輸入神經網絡特徵圖並將其並行激活，使其能夠實現乘法和累加（MAC）的功能。
這項研究提出了一個使用6T SRAM進行多位元MAC操作的SRAM-CIM巨集，最高能在CNN應用提供8位元輸入，8位元權重和20位元輸出精度，使用（1）位元式權重MAC（WbwMAC）以增大感測裕度以提高輸入、權重和輸出精度，（2）6T區域計算單元（LCC），提供緊湊面積和針對工藝變化的可靠讀取，（3）位元式權重之低MAC偵測讀取電路（Wbw-LMAR），基於軟硬體協同設計，以改進能源效率（EFMAC）。製造的28nm 64Kb 6T SRAM-CIM巨集實現了最高8位元輸入、8位元權重（8bIN-8bW）MAC操作，具有目前SRAM-CIM工作中最高的輸出精度，達到運算時間4.1-8.4ns和能源效率11.5-68.4 TOPS/W。

In recent years, the rapid development of deep neural networks and the widespread use of various edge devices have greatly increased the amount of data transmission. However, the process of moving data between the CPU and memory consumes most of the energy in the traditional Von Neumann architecture, which is called the Von Neumann bottleneck. Therefore, computing-in-memory has become a development goal to solve this bottleneck.
Computing-in-memory can have both calculation and storage capabilities. Performing calculations before reading data can directly transfer results to reduce the process of moving large amounts of data. In order to achieve the above objectives, the design idea of this work is to input the neural network feature map and activate it in parallel, so that it has the functions of operation multiplication and accumulation (MAC).
This work presents an SRAM-CIM macro using 6T SRAM for multibit MAC operations with up to 8b-IN, 8b-W, and 20b output precision for CNN applications using (1) weight bit-wise MAC (WbwMAC) operations to enlarge the sensing margin and enhance IN/W/OUT precision, (2) a 6T local-computing-cell (LCC) for compact area and robust read against process variations, (3) a weight bit-wise low-MAC aware readout (Wbw-LMAR) scheme based on software-hardware co-design to improve EFMAC. A fabricated 28nm 64Kb 6T SRAM-CIM macro demonstrated 8bIN-8bW MAC operations with the highest output accuracy in current SRAM-CIM works, reaching an access time of 4.1-8.4ns and Energy efficiency 11.5-68.4TOPS / W.

致謝..........................................i
摘要..........................................ii
Abstract..........................................iii
Contents..........................................v
List of Figures    ..........................................viii
List of Tables    ..........................................x
Chapter 1    Introduction..........................................1
1.1 Memory Landscape..........................................1
1.1.1 RAM..........................................3
1.1.2 CAM..........................................4
1.1.3 ROM..........................................4
1.1.4 Programmable NVMs..........................................5
1.2 Von Neumann bottleneck..........................................6
1.3 Computing-in-Memory (CIM)..........................................7
Chapter 2    Introduction for SRAM..........................................10
2.1 Introduction for Conventional 6T SRAM..........................................10
2.1.1 Structure of SRAM    ..........................................10
2.1.2 Write Operation and Write Margin..........................................11
2.1.3 Read Operation..........................................12
2.2 Introduction for Hierarchical Bitline 6T SRAM..........................................13
2.2.1 Structure of Hierarchical Bitline 6T SRAM Array..........................................13
2.2.2 Write Operation..........................................15
2.2.3 Read Operation..........................................16
Chapter 3    Previous Work..........................................18
3.1 10T SRAM-CIM with Binary Weight Analog Computing..........................................18
3.2 6T SRAM-CIM with Multi-bit Weight Word-wise Analog computing    ..........................................20
3.3 Twin-8T SRAM-CIM with Multi-bit Weight Word-wise Analog computing..........................................24
3.4 8T SRAM-CIM with Binary Weight Analog Computing..........................................26
Chapter 4    Proposed Circuit Schemes and Analysis..........................................29
4.1 Proposed Computing-In-Memory Circuit Scheme..........................................30
4.1.1 Proposed CIM Structure..........................................30
4.1.2 Proposed Computing-In-Memory Operation..........................................33
4.1.3 Proposed weight bit-wise low-MAC aware readout (Wbw-LMAR) scheme..........................................37
4.2 Analysis and Comparison..........................................40
4.2.1 Proposed Sensing Scheme Analysis..........................................40
Chapter 5    Macro Implementation..........................................44
5.1 Floor Plan of SRAM-CIM Macro..........................................44
5.2 Design for Test chip..........................................45
Chapter 6    Experimental Results and Conclusion..........................................47
6.1 Measured Performance..........................................47
6.2 Comparison to Previous Work    ..........................................49
6.3 Conclusions and Future Work    ..........................................51
Reference..........................................53

                                

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