摘要

為了迎合當前CMOS元件的發展方向，在本次的實驗中，我們使用鍺作為通道材料，並結合結晶態高介電常數材料ZrTiO4與介面層材料Yb2O3作為閘極介電層，製成鍺電容元件。
在第一個主題中，我們研究Yb2O3作為鍺電容元件之閘極介電層的特性。由XPS化學成分分析的結果可以得知在Yb2O3與鍺基板之介面形成了鍺金屬氧化物YbGeOx，穩定的鍺金屬氧化物YbGeOx對於鍺基板表面有良好的保護，所以之後的電性量測分析可以發現，無論是漏電流、頻散現象以及介面缺陷密度均有不錯的表現。
在主題一中證明了Yb2O3確實可以有效保護鍺基板表面，於是我們在主題一的基礎之上，使用ZrTiO4/Yb2O3堆疊結構作為鍺電容元件之閘極介電層，希望能更進一步提升元件特性。在XRD結晶繞射分析中，可以得知經過600 oC RTA之後元件確實形成了結晶態Orthorhombic ZrTiO4。電性方面，由於結合了Orthorhombic ZrTiO4使得元件之等效氧化層厚度相較於主題一的實驗可以更進一步降低。另外因為Yb2O3介面層可以有效改善鍺基板的介面品質，且ZrTiO4/Yb2O3堆疊結構可以與主題一在相同等效氧化層厚度之情況下有較厚的物理厚度，所以在漏電流方面也有更好的表現。最後，可靠度量測中顯示，ZrTiO4/Yb2O3堆疊結構的鍺電容元件的PBTI表現雖然比單層Yb2O3的鍺電容元件表現差，這是由於ZrTiO4結晶化後在晶界的部分會有缺陷產生，使得電子注入後易被捕捉。不過整體來說，由於ZrTiO4/Yb2O3堆疊結構的元件有Yb2O3介面層的保護，所以仍使元件呈現出良好之PBTI表現。綜合以上結果，我們認為結晶態高介電常數材料ZrTiO4結合稀土族氧化物介面層Yb2O3之堆疊結構作為鍺電容元件之閘極介電層材料具有相當大的潛力。

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