多裸晶封裝是現今科技的新趨勢，但跨裸晶時脈訊號同步也是伴隨而來的難題。跨裸晶時脈訊號同步的難題在於將各個裸晶的時脈訊號網路連成一個同步的網路比單純設計一個裸晶內部的時脈訊號網路困難許多。各個裸晶大多是獨立設計，系統整合商難以掌握裸晶內部的狀況。因此難以達到跨裸晶時脈訊號同步。在這篇論文中，我們通過結合鎖延遲迴路(DLL)來校正，以達成全晶片同步的效果。在每個裸晶中植入一個鎖延遲迴路，此鎖延遲迴路可由鎖延遲迴路編譯軟體產生，以便同步校正各個裸晶中的時脈訊號延遲(從時脈訊號源到各個正反器的時脈訊號端口)。我們也建構出一圖形使用者介面，以便於使用者簡單操作我們的自動化方案。另外圖形使用者介面也能產生此自動化方案所需的控制器。
此自動化方案的優點為可以獨立設計每個晶片的時脈訊號網路，並在晶片工作時，使得整個晶片的時脈訊號偏差量仍可動態的反應其工作環境並達到最小化。在研究實驗中，我們使用台積電90奈米製程來實現虛擬的四裸晶晶片，並以此虛擬的四裸晶晶片做實驗，應用此方案後，時脈訊號偏差量 (Clock Skew) 可從233皮秒 (ps) 降至34皮秒。在電壓改變的狀況下，四裸晶晶片仍可維持微小的訊號偏差量。在鎖延遲迴路鎖定後，改變的電源電壓，最大的時脈訊號偏差量為45皮秒。

Multi-die packaging is now a new trend in today's technology, but chip-level clock synchronization is a complication. The challenge of synchronizing the clock network across multi-die is harder than synchronizing the clock network within a die. Most of the dies are design independently, so that system integrators cannot control the clock network in every die. It is difficult to achieve chip-level clock synchronization. In this thesis, we use Delay-Locked Loops (DLLs) to reach the goal. A DLL is inserted in each die, which can be generated by a DLL compiler, to dynamically correct the clock latency (from a clock source to each clock port of flip-flop) in every functional die. We have also constructed a graphical user interface that allows users to easily manipulate our automatic scheme. In addition, the graphical user interface can generate the controller needed for this automatic scheme.
The advantage of this automatic scheme is that the clock network of each chip can be designed independently. When the chip is in operation, the clock skew of the whole chip can still be dynamically responded to and minimized. In the research experiment, we use TSMC's 90-nanometer process to build a pseudo 4-die design. After applying this scheme, the clock skew can be reduced from 233ps down to 34ps. In the case of voltage variation, 4-die IC can still maintain a slight clock skew. After the DLLs locked, the maximum clock skew is 45ps under power supply variation.

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