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研究生: 蘇慶峰
Su Ching-Feng
論文名稱: 對於單晶片系統提出以重覆使用核心為導向的設計範例
A Core-Centric Design Paradigm for System-on-a-Chip
指導教授: 吳中浩
Wu Chung Hao
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2000
畢業學年度: 88
語文別: 英文
論文頁數: 89
中文關鍵詞: 單晶片系統重複使用核心智慧財產有限狀態機和資料路徑高階合成
外文關鍵詞: SOC, reuse, core, IP, FSMD, High-Lvel Synthesis
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  • 在這篇論文中,我們呈現以零件核心為導向(core-centric)的設計範例。 我們提出一個重複使用零件核心(IP reuse)的方法以及設計流程。 藉著這個設計流程,我們可將以簡單的重複使用已設計好的零件核心(core),以便將以高階語言為規格的設計轉換到晶片的佈局。
    在第一章中我們簡介了最近晶片設計的趨勢.由於製程的進步,使得單位矽晶片的容量每18個月成長一倍。這意味著設計著可將更複雜的設計放入一片晶片中。這也表示設計者設計複雜系統所需的時間相對於系統複雜度的成長已正在減少中。這代表著在矽晶片容量與設計的產能的隔閡已隨著矽晶片的容量一起增加。這些原因驅使一些設計自動化的業者正朝向如何重複使用複雜零件的方法上努力。我們將會在這篇論文中提出如何重複使用複雜零件的方法與流程。

    。第二章中我們介紹目前在業界中幾個可幫助設計者重複使用零件(IP reuse)的電腦輔助工具之限制及優缺點。最近已有一些零件重複使用的業者提出一些電腦輔助設計的工具像是AMICAL, CADDY-Π, ALOHA, XE。AMICAL系統的缺點是使用者必須指定要用的零件(component),這表示此系統無法自動的分配(allocate)零件。CADDY-Π系統的缺點是沒有一個方法將已設計好的零件匯入此系統ALOHA系統在合成時無法自動的選擇零件。XE系統可以做到上述系統所做不到的功能。

    第三章我們提出了以零件核心為導向的設計方法與流程。我們在3.1中將討論建立核心導向方法與流程的動機與考慮。在3.2中我們將對所建議的設計流程提出概念性的說明。在3.3中我們將描述高階語言的規格和如何的轉換這個規格。在3.4中我們將介紹核心導向的合成方法。最後我們將在3.5中呈現重複使用處理器核心的設計方法。

    最後我們在第四章中以聲音辨識(speech recognition)為範例來驗證我們的設計方法確實是可已有效的縮短設計的時間。我們以聲音辦別的應用來驗證我們的方法。在4.1中我們先給一個概括性的說明。在4.2中我們描述聲音辨識應用的核心定義程序。在4.3中我們呈現實例驗證。在4.4中我們呈現出實例驗證的結果


    In this thesis, we present a core-centric design paradigm for System-on-a-Chip (SoC) designs. We present a design methodology and flow that is able to convert design specifications into chip layouts by automatically reused existing cores. Case studies targeted to speech recognition applications have been conducted to demonstrate the viability of the proposed core-centric design paradigm. The results show that the proposed core-centric design paradigm can significantly shorten the chip development time by reusing silicon-proof soft cores.

    Abstract 2 Contents 3 List of Figures 4 Chapter 1 : Introduction 6 Chapter 2 : Related Work 8 Chapter 3 : A Core-Centric Design Paradigm 10 3.1 Motivation and Consideration 11 3.2 Overview of the Design Flow 13 3.3 High-level Specification and Transformation 15 3.3.1 Target Architecture 16 3.3.2 C-based Specification 17 3.3.3 C-to-VHDL Transformation 18 3.4 The Core-Based Synthesis Method 20 3.4.1 Usage-based Component Library 21 3.4.2 The Reuse-Automation Synthesis Method 24 3.5 Design Method for Reusing Processor Core 28 Chapter 4 : Case Study 30 4.1 Overview 30 4.2 Core Definition and Development 32 4.3 The GJ and DTW Development Using the Core-Centric Design Method 34 4.3.1 The Experimental Design Flow 34 4.3.2 The Gauss-Jordan Method 36 4.3.3 The System Architecture 38 4.3.4 Module Design and System Integration 40 4.3.4.1 The Interface Specification 40 4.3.4.2 The Load Module 43 4.3.4.3 The Store Module 44 4.3.4.4 The GJ Module 45 4.3.4.5 System Integration 47 4.3.4.6 The GJ Design by Reusing the PIC Core 47 4.4 The Results 49 Bibliography 53

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