近年來，由於半導體製程與積體電路設計技術的進步，一個
複雜的系統已可以整合在一個晶片上，而此一晶片則被通稱

為系統晶片 (System-on-a-Chip)。利用事先設計並驗證過的

設計模組以設計系統晶片，將成為積體電路 (IC) 設計新趨

勢。新的設計方式將 IC 設計產業區分成為核心電路提供

者 (Core Provider)\ 與使用者 (Core User)。為避免製

造晶片後的測試成為整體流程中的瓶頸，不僅是設計模組本

身，還有測試模組的測試向量 (Test Pattern) 都須重複使

用；除此之外，測試標準化也是重要的工作之一。目前正值

發展中的 IEEE P1500 Standard for Embedded Core Test

(SECT) 組織，目的便是在於訂立一個應用於系統晶片測試

的標準，而這個標準將幫助解決系統晶片的測試問題，同時

亦一套``隨插即用''的測試方法，利用這個方法，便可得心

應手地完成系統晶片測試的工作。

在這篇論文當中，我們提出一個具備標準測試介面 (Test

Wrapper) 的系統晶片測試控制架構。不論是序列或平行的測

試傳輸途徑 (Test Access Mechanism)，都可以應用在這個架

構下，以達成測試的目的。若使用平行的測試傳輸途徑，雖然

可以縮短測試時間，但卻需要較多的額外硬體成本。論文中所

提出的測試控制架構相當簡單，而且額外硬體成本非常低。此

外，一個自動化產生測試控制電路的工具亦被發展，這個工具

能自動產生可合成的硬體描述語言、合成用的指令稿和驗證控

制電路的測試檔案。最後，一個應用此測試控制架構的測試晶

片被實現，測試晶片本身包含了四個核心電路、六個嵌入式記

憶體以及三個記憶體內置自我測試電路 (Memory BIST)，整體

的額外硬體成本僅佔原來晶片的百分之六左右。

With the advent of deep submicron technology and system-on-chip
(SOC) design methodology, complex systems can be integrated into

a single chip. SOC designs which usually consist of reusable

cores from multiple resources are becoming a trend of IC

industry. However, complex designs also pose more testing

problems than the conventional VLSI designs. To prevent the

testing from becoming the bottleneck of SOC manufacturing

process, not only the cores but also the core tests should be

reusable. Therefore, the IEEE P1500 standard is being proposed

to make SOC and test reuse in a `play-and-plug' way.

We propose a test control architecture for SOC designs with IEEE

P1500 test wrapper in this thesis. This architecture can

support both serial interface layer and parallel test access

mechanisms. The major advantages of the test control mechanism

have low area overhead and protocol use to handle the test

process is simple. A compiler for the test controller is

implemented. It generates the synthesizable RTL code, synthesis

script of the RTL code and the test bench used to verify the

test control architecture. This design has been applied to an

industrial practice. The test chip is composed of four embedded

logic cores, six embedded SRAM cores and some user-defined

logics. Experimental results show that the area overhead of the

test controller, the parallel test access mechanism and the

test wrapper is low, which about $6.14\%$ in total.

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