評估場可程式化閘級陣列測試電路之統計延遲缺陷涵蓋率

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研究生：	廖祥傑 Hsiang-Chieh Liao
論文名稱：	評估場可程式化閘級陣列測試電路之統計延遲缺陷涵蓋率 Evaluating Statistical Delay Defect Coverage for FPGA Test Configurations
指導教授：	吳誠文 Cheng-Wen Wu 劉靖家 Jing-Jia Liou
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	51
中文關鍵詞：	延遲測試、評估、缺陷、場可程式化閘級陣列
外文關鍵詞：	delay testing, evaluate, defect, FPGA
相關次數：	點閱：3 下載：0
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場可程式化閘級陣列（Field Programmable Gate Array）表現問題的測試，對於日新月異的科技來講已經變成一個重要的任務。在開發測試方法的過程中，一個有效的評估工具將扮演一個重要的角色。在這篇論文中，我們發表了一個場可程式化閘級陣列錯誤模擬器的工具。這個工具可以報告測試方法對於隨機分佈於FPGA中延遲缺陷的涵蓋率。此外，這個工具還可確認目前測試沒有包含到的路徑，且可用以更進一步地改善測試電路集合的品質。

Testing for FPGA performance problems has become an important task for ever-increasingly advanced technology. To develop testing methodologies, an effective evaluation tool should play an important role in this process. In this thesis, we present an FPGA fault simulation tool (FFAST).
This tool can report coverages of randomly distributed multiple defects causing delay faults in FPGAs. FFAST can also identify paths (test configurations) which are not covered in the current tests. This information can be used to further improve the quality of test configuration sets.

Introduction                                            6
1 Background . . . . . . . . . . . . . . . . . . . . . .6
2 Motivation . . . . . . . . . . . . . . . . . . . . . .7
3 Organization. . . . .  . . . . . . . . . . . . . . . .7
Previous Work                                           9
1 FPGATest . . . . . . . . . . . . . . . . . . . . . . .9
2 FaultSimulation . .. . . . . . . . . . . . . . . . . 10
3 FaultModels . . . . .  . . . . . . . . . . . . . . . 11
4 FPGAArchitectures . . . . . . . . . . . . . . . . . .12
4.1 Hierarchical-style FPGA Architecture . . . . . . . 12
4.2 Island-style FPGA Architecture . . . . . . . . . . 14
The Proposed Fault Simulator                           16
1 FFAST Simulation Environments . . .  . . . . . . . . 16
2 Segment Coverage . . . . . . . . . . . . . . . . . . 17
3 Statistical Delay Defect Coverage . . . . .. . . . . 20
3.1 Statistical Defect Models . . . . . . . . . . . . .21
3.2 Effective SDDC . . . . . . . . . . . . . . . . . . 22
3.3 Failed Path Searching . . . . . . . . . . . . . . .22
4 SimulationFlow. . . . . . . . . . . . . . . . . . . .24
5 Implementation . . . . . . . . . . . . . . . . . . . 26
5.1 Switch Matrix Modeling . . . . . . . . . . . . . . 27
5.2 Defect Model . . . . . . . . . . . . . . . . . . . 27
5.3 Failed Paths Decision . . . .  . . . . . . . . . . 28
Experimental Results                                   31
1 Test Configurations for Interconnect Testing . . . . 31
2 Test Configurations for Universal FPGA Delay Testing 33
3 Test Configurations for FPGA BIST . . . . . . . . . .34
4 CPU Time Usage . . . . . . . . . . . . . . . . . . . 40
Conclusions                                            44
A The List of All Commands                               45
B File Formats                                           46
B.1 Architecture File . . . . . . . . . . . . . . . . . .46
B.2 Configuration File . .. . . . . . . . . . . . . . . .47
B.2.1 Route File . . . . . . . . . . . . . . . . . . . . 47
B.2.2 Place File . . . . . . . . .. . . . . . . . . . . .47
B.3 Defect File . . . . . . .. . . . . . . . . . . . . . 48
B.4 Map File . . . . . . . .  . . . . . . . . . . . . .. 48
B.5 Specification File . . . . . . . . . . . . . . . . . 48
B.6 Simulation Report . . . . . . . . . . . . . . . .  . 49

                                

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