具有製程、電壓、溫度不敏感性電壓-時間-電壓轉換器之十二位元二階雜訊塑形連續漸進式類比數位轉換器

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研究生：	陳志誠 Chen, Chih-Cheng
論文名稱：	具有製程、電壓、溫度不敏感性電壓-時間-電壓轉換器之十二位元二階雜訊塑形連續漸進式類比數位轉換器 A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	李泰成 Lee, Tai-Cheng 謝秉璇 Hsieh, Ping-Hsuan 陳佳宏 Chen, Chia-Hung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2021
畢業學年度：	110
語文別：	中文
論文頁數：	69
中文關鍵詞：	過採樣、雜訊塑形、連續漸進式類比數位轉換器
外文關鍵詞：	oversampling, noise-shaping, SAR ADC
相關次數：	點閱：2 下載：0
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本論文提出一個具有製程、電壓、溫度不敏感性電壓-時間-電壓轉換器之十二位元二階雜訊塑形連續漸進式(successive-approximation register, SAR)類比數位轉換器(analog-to-digital converter, ADC)。
本論文使用了電壓-時間-電壓(Voltage-Time-Voltage, V-T-V)轉換器提供了精準的開環增益，由於僅依靠電容與電流比例，其增益本質上對於製成、電壓與溫度(Process-Voltage-Temperature, PVT)具有不敏感性，因此並不需要教正即可實現理想的雜訊轉換函數 (noise transfer function, NTF)。此外，V-T-V轉換器只消耗動態功率。透過使用元件比例設計與動態功耗方式，所提出的ADC具有抵抗PVT變異與良好功率效益的特性。
為了驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，核心電路面積為429.7 x 90.7um2，在1伏特電源電壓及1千萬赫茲取樣頻率操作下，此晶片在625千赫茲輸入頻寬實現之SNDR為73.8dB，其對應的ENOB為12-bit，功率消耗為71.4微瓦，而等效的Walden figure of merit (FOMW)為14.2fJ/conversion-step，Schreier figure of merit (FOMS)為173.2dB。

This thesis presents a 12-ENOB second-order noise shaping successive-approximation register (NS SAR) analog-to-digital converter (ADC) with PVT-insensitive voltage-time-voltage (V-T-V) converter.
The proposed NS SAR ADC uses the V-T-V converter to provide an accurate open-loop gain stage for active residue process. By relying on the capacitor and current ratio only, the gain of V-T-V converter is inherently PVT-insensitive. Therefore, no calibration is needed and an aggressive noise transfer function (NTF) can be realized. Moreover, the V-T-V converter consumes only dynamic power. By using ratio design and dynamic manner, the proposed ADC is PVT-insensitive and energy efficient.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 429.7 x 90.7um2. At 1V supply voltage and 10MS/s sampling rate, the ADC achieves the SNDR of 73.8dB and the corresponding ENOB is 12-bit at the input bandwidth of 625kHz. It consumes 71.4µW power totally, resulting in the Walden figure of merit (FOMW) of 14.2fJ/conversion-step and Schreier figure of merit (FOMS) of 173.2 dB, respectively.

Abstract-----ii
Content-----iii
List of Figures-----vi
List of Tables-----ix
Chapter 1 Introduction-----1
1 Motivation-----1
2 Architecture selection-----1
3 Target Specifications-----3
4 Thesis Organization-----5
Chapter 2 Basic Concept of ADC-----5
1 Sampling Theorem-----6
2 Resolution-----6
3 Quantization Error-----7
4 Offset Error-----8
5 Gain Error-----9
6 Differential Nonlinearity-----10
7 Integral Nonlinearity-----11
8 Signal-to-Noise Ratio-----12
9 Signal-to-Noise and Distortion Ratio-----13
10 Spurious-Free Dynamic Range-----13
11 Effective Number of Bits-----13
12 Figure of Merit-----13
Chapter 3 System Level Overviews of ADCs-----14
1 Top level-----14
1.1 SAR ADC-----15
1.2 Delta Sigma Modulator (DSM)-----16
1.3 Noise Shaping SAR ADC (NS SAR ADC)-----17
2 Sample and Hold (S/H)-----18
2.1 On-Resistance of MOSFET switch-----19
2.2 Charge Injection-----20
2.3 Clock Feedthrough-----21
2.4 kT/C Noise-----21
3 Comparator-----22
3.1 Input Referred Offset-----23
3.2 Kickback Noise-----24
4 Capacitive DAC (C-DAC)-----25
4.1 Mismatch of Capacitors-----26
4.2 Parasitic Capacitance-----27
5 Asynchronous SAR Logic-----27
6 Structure of Noise Shaping SAR ADC-----28
6.1 Cascaded Integrator Feed-Forward (CIFF)-----29
6.2 Error-Feedback (EF)-----29
7 Implementation of Residue Process-----31
8 Summary-----34
Chapter 4 Circuit Design Considerations-----35
1 Differential ADC-----35
2 Implementation of Noise Shaping-----36
2.1 Signal Model-----36
2.2 Non-Ideal Effect-----37
3 Sample and Hold (S/H)-----38
4 Comparator-----39
5 CDAC Switching-----40
6 Summary-----42
Chapter 5 Circuit Implementation of Proposed Noise Shaping SAR ADC-----42
1 Architecture of Proposed NS SAR ADC-----42
2 Architecture of Proposed V-T-V converter-----44
3 Design of V-T-V converter and SC FIR capacitors-----48
4 Design of Sample and Hold (S/H)-----50
5 Design of Comparator-----51
6 Design of Capacitive DAC (C-DAC)-----52
7 Pre-Layout and Post-Layout Simulation-----53
8 Summary-----55
Chapter 6 Experimental Results-----55
1 Measurement Environment Setup-----55
2 Chip Micrograph-----56
3 Measurement Results-----56
3.1 SAR ADC w/o Noise Shaping-----57
3.2 SAR ADC w/ Noise Shaping-----58
4 Performance Discussion-----60
5 Performance Summary and Comparison-----62
6 Summary-----64
Chapter 7 Conclusion and Future Work-----64
1 Conclusion-----64
2 Future Work-----64
Bibliography-----66

                                

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