數位處理器的效能依賴於加法器的速度，在過去，高速加法器持續被發明出來，其中CLA(Carry Look-ahead Adder)是最廣為人知的快速加法器，最近幾年，CLA改良的版本已經被提出稱為MCLA(Modified Carry Look-ahead Adder)，無論CLA或MCLA，無論CLA或MCLA，其運算的速度的瓶頸在於進位問題。

　　在本篇論文中，提出一種新的加法器稱為CT-MCLA(Carry Through - Modified Carry Look-ahead Adder)，它能解決進位問題並使用較少的面積，CT-MCLA且結合了CTA和MCLA，CT-MCLA使用進位通過的技術解決進位問題以獲得較高的速度。

　　本篇論文所提出的CT-MCLA和Yu-Ting Pai and Yu-Kumg Chen所提出的MCLA作了比較，從8-bit到64-bit，結果發現本篇論文所提出的方法有效的把電路的面積減少5~10%，延遲時間在8-bit會加長6%，但在其餘16-bit至64-bit縮短約7~9%，整體的AT2提升約3~14%。

The performance of digital processor depends on the speed of adder. In the past, high-speed adders have been continuous invented. Among that, CLA (Carry Look Ahead Adder) was the most well known high-speed adder. In recent years, an improved version of CLA called MCLA (Modified Carry Look Ahead Adder) was presented. However, carry propagation was still the bottle neck in both CLA and MCLA.
In this thesis, a new type adder called CT-MCLA (Carry Through - Modified Carry Look Ahead Adder) is proposed to improve the carry propagation issue and uses less area. Combined MCLA, the proposed adder uses the carry through technique to overcome carry propagation issue for obtained higher speed.
The simulation results of proposed CT-MCLA from 8-bit to 64-bit improve area of 5~10% compared with MCLA. The speed is improved –6%~9%. The product of area size and time square (AT2) is also improved 3~14%.

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