一個使用單極性零交錯偵測之十二位元連續近似輔助管線式類比數位轉換器

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研究生：	張永德 Chang, Yung-Te
論文名稱：	一個使用單極性零交錯偵測之十二位元連續近似輔助管線式類比數位轉換器 A 12-bit zero-crossing-based pipelined-SAR ADC with single-polarity transfer
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	李泰成 Lee, Tai-Cheng 張順志 Chang, Soon-Jyh 洪浩喬 Hong, Hao-Chiao
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	107
語文別：	英文
論文頁數：	84
中文關鍵詞：	零交錯偵測、連續近似輔助管線式類比數位轉換器、類比數位轉換器
外文關鍵詞：	zero-crossing-based, pipelined-SAR, ADC
相關次數：	點閱：3 下載：0
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本論文提出一個使用單極性傳遞之連續近似輔助零交錯偵測管線式(zero-crossing based pipelined-SAR)十二位元類比數位轉換器(ADC)。
為達到高速度的取樣頻率並維持良好功率消耗表現，本論文所提出之類比數位轉換器以管線式操作，並使用了單極性傳遞之零交錯偵測取代傳統的乘積式數位類比轉換器(Mutiplying digital-to-analog converter, MDAC)。提出的單極性傳遞之零交錯偵測可以有效地降低管線式類比數位轉換器中的MDAC的功率消耗，在單極性傳遞的操作下可以改善傳統雙端(differential)傳遞所造成的訊號偏移，進而提高能源效率和類比數位轉換器的線性度。
為驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，核心電路面積為159×245μm2，在1伏特電源電壓及40百萬赫茲取樣頻率操作下，此晶片在低頻率訊號輸入時實現之SNDR為為56.9dB，其對應的ENOB為9.2bit，功率消耗為430微瓦，等效的figure of merit (FoM)為18.3fJ/conversion-step。

This thesis presents a 12-bit zero-crossing-based pipelined-SAR (successive-approximation register) analog-to-digital converter with single-polarity transfer.
The proposed ADC operates on pipelined mode and uses single-polarity transfer zero-crossing detection instead conventional multiplying digital-to-analog converter to achieve a higher operation speed and save power. The proposed single-polarity transfer zero-crossing detection can improve the power consumption from MDAC in pipelined ADC effectively and the error sources from the differential mode, which can save more power and increase linearity of the ADC.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 159×245μm2. At 1 supply voltage and 40MS/s sampling rate, the ADC achieves SNDR from 56.9dB corresponding ENOB from 9.2 bit at low frequency input and consumes 430uW power, resulting in a figure of merit (FoM) from 18.3 fj/coversion-step.

Abstract    iii
Content    iv
List of Figures    viii
List of Tables    xii
Chapter 1    Introduction    1
1    Architecture Selection    2
2    Performance Metrics of SAR ADC    4
2.1    Nyquist Criterion    4
2.2    Resolution    4
2.3    Quantization Error    5
2.4    Offset and Gain Error    6
2.5    Differential Nonlinearity    6
2.6    Integral Nonlinearity    7
2.7    Signal-to-Noise Ratio    7
2.8    Signal-to-Noise and Distortion Ratio    8
2.9    Spurious-Free Dynamic Range    8
2.10    Effective number of bits    8
2.11    Figure of Merit    9
3    Target Specifications    9
Chapter 2    Successive Approximation Register ADC Overview    11
1    Introduction    11
2    Operation Procedure of Conventional SAR ADC    12
3    Considerations of Sample and Hold    13
3.1    Charge Injection    14
3.2    Clock feedthrough    15
3.3    KTC Noise    15
3.4    Sampling Speed    16
4    Considerations of Capacitive DAC    17
4.1    DAC Parasitic Capacitance    18
4.2    DAC Capacitor Mismatch    19
4.3    Settling Time    20
5    Considerations of Comparator    21
5.1    Input Offset    22
5.2    Kickback Noise    23
6    SAR Control Logic    24
7    Summary    25
Chapter 3    Pipelined ADC Overview    27
1    Introduction    27
2    Operation Procedure of Pipelined ADC    28
3    Redundancy Bit    29
4    Considerations of Sub-ADC    30
5    Considerations of Multiplying DAC (MDAC)    31
5.1    Opamp DC Gain Requirements    33
5.2    Opamp Bandwidth Requirements    34
6    Digital Error Correction Logic    34
7    Summary    36
Chapter 4    Circuit Design Considerations    37
1    Differential ADC    37
2    Stage Resolution Distribution in Pipelined-SAR    38
2.1    Timing distribution    39
2.2    Opamp DC Gain Requirements    40
2.3    Opamp Bandwidth Requirements    40
3    Sample and Hold    42
4    CDAC Switching Energy    43
5    Comparator    46
6    Zero-Crossing-Based Circuits    46
6.1    Overshoot from Time-Delay    48
6.2    Fully Differential ZCBC    49
6.3    Proposed ZCBC with Single-Polarity Transfer    52
7    Summary    55
Chapter 5    Circuit Implementation of Pipelined-SAR ADC    56
1    Architecture of Proposed Pipelined-SAR ADC    56
2    Design of Sample and Hold    58
3    Design of Capacitive DAC    59
4    Design of Comparator    60
5    Design of Foreground Calibration    61
6    Design of ZCBC with Single Polarity Transfer    63
6.1    Design of Zero-Crossing Detector(ZCD)    64
6.2    Design of Current Source    67
7    Pre-Layout and Post-Layout Simulations    68
8    Summary    69
Chapter 6    Measurement Results    70
1    Measurement Environment Setup    70
2    Chip Micrograph    71
3    Static Performance    72
4    Dynamic performance    73
5    Performance Discussion    74
6    Performance Summary and Comparison    78
Chapter 7    Conclusion and Future Work    81
1    Conclusion    81
2    Future Work    81
Bibliography    82
                                

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