隨著高壓製程的進步，功率積體電路的應用越來越廣，對於功率元件的需求也與日俱增。絕緣閘雙載子電晶體(Insulated Gate Bipolar Transistor，IGBT)是具有高電流、低導通阻抗與高崩潰電壓的最佳候選之一。然而IGBT與積體電路一起整合在晶片內需要橫向(Lateral)的元件結構，這面臨的主要問題，如寄生雙載子電晶體導通造成嚴重的基板電流，使積體電路操作會有閂鎖(latch-up)的風險。在抑制基板電流的設計方面，我們利用接面絕緣技術(Junction Isolation，JI)取代矽覆絕緣技術(Silicon-on-Insulator，SOI)的元件架構來降低成本以及避免SOI散熱不好的問題。因此，我們利用0.5μm高壓製程技術與一次磊晶(Epitaxy)的技術，提出一個新型的接面絕緣型橫向絕緣閘雙載子電晶體(Junction Isolation Lateral IGBT，JI-LIGBT)架構，藉由掩埋層結構(Buried Layer，BL)來抑制基板電流。我們成功的設計出崩潰電壓200V與700V的JI-LIGBT，在元件相同崩潰電壓條件下，設計結合準垂直擴散金氧半場效應電晶體(Quasi-Vertical Diffused Metal-Oxide-Semiconductor Field Effect Transistor，QVDMOSFET)來提高飽和電流，使元件導通電流與基板電流有最佳化的設計。
為了使應用範圍更加廣泛，設計一個200V應用的接面絕緣技術之N型橫向絕緣閘雙載子金氧半電晶體，本論文製作具有一部分N型掩埋層與多通道結構，以加強抑制基板電流。這個摻雜濃度較高的N型掩埋層被設計在元件陽極的下端，量測結果證明此結構可以有較低的基板電流且具有大於160V的操作電壓應用。
由於功率積體電路常常操作在嚴苛的環境。在高溫情況下改善元件的穩定特性是必要的，我們設計NPN陽極的架構在本體矽之接面絕緣技術橫向絕緣閘雙載子金氧半電晶體，比較三種元件結構在不同溫度情況下元件關斷狀態的漏電流密度分佈。本論文提出的架構改善了關斷狀態的漏電流。此外，設計P型頂環延伸至NPN陽極的架構，不僅改善崩潰電壓至大於900V，更可以減少基板電流以確保在高溫的穩定性。

Based on the progress of the high voltage process, power integrated circuit has more and more widely applications. The demand for power components is also increasing. Insulated-gate bipolar transistor (IGBT) is one of the best candidates for a high current, low on-resistance and high breakdown voltage application. However, to integrate the IGBT with other low-voltage control circuits requires a lateral architecture, an LIGBT, within the silicon wafer. However, the conduction of the LIGBT parasitic bipolar transistor may cause a serious substrate current. So that such an integrated circuit will face the risk of latch-up effect. In order to suppress the substrate current without using the high cost and heat dissipation troubled silicon-on-insulator (SOI) technology, a junction isolation technology (JI) design is proposed and verified in this dissertation that uses a 0.5μm high voltage process technology and an epitaxy technology. A junction isolation lateral IGBT (JI-LIGBT) is proposed to suppress the substrate current with breakdown voltage greater than 700V. In addition, the quasi-vertical double diffusion metal-oxide-semiconductor field effect transistor (QVDMOSFET) is included to improve the saturation current.
In order to make the application more extensive, we designed a 200V JI-LIGBT with an N-type buried layer (BL) and multi-channel structure to more suppress the substrate current. Measurement results show that this structure has a lower substrate current and its operating voltage is higher than 160V.
Since power integrated circuits are often operated in harsh environments. The high temperature DC characteristics of a high-voltage bulk Si lateral insulated-gate bipolar transistor in junction isolation (JI-LIGBT) technology is studied intensively in this dissertation. The current density distribution in the off-state at different temperatures of three types of device structure is compared. By using the Quasi-vertical DMOSFET (QVDMOS or multi-channel, MC) structure, the electron injection from the channel into the n-drift region is significantly enhanced, and the current density is improved. In addition, by extending the p-top layer to the NPN anode not only improves the breakdown voltage but also reduces the substrate current as well as ensures high temperature stability.

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