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研究生: 蔡明蒼
Tsai, Ming-Tsang
論文名稱: 可完全相容於邏輯製程之高壓接點閘極金氧半場效電晶體
High Voltage Contact Gate MOSFET (CG-MOSFET) with Fully CMOS Logic Compatible Process
指導教授: 金雅琴
King, Ya-Chin
林崇榮
Lin, Chrong-Jung
口試委員: 金雅琴
King, Ya-Chin
林崇榮
Lin, Chrong-
蔡銘進
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 61
中文關鍵詞: 崩潰電壓邏輯製程導通阻值
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  • 近年來,隨著能源議題的看重,電力電子和功率元件的發展亦成為關鍵之一,而如何獲得良好的耐壓能力與導通阻值的權衡和如何降低製作成本一直是功率元件的研究發展重點,儘管許多研究發表只需少數光罩即可完成,但仍為特殊製程,需藉由打線接合(Wire bonding)技術將功率元件和主要電路部分連接,因此在成本降低部分仍然受限。
    本論文提出一個可整合於互補式金氧半邏輯製程的20伏特等級功率元件,稱為接點閘極金氧半場效電晶體(Contact Gate MOSFET,CGMOS),因為此元件不需漂移區(Drift region)光罩且不需額外的打線接合技術,故可大幅降低製作成本。藉由T-CAD軟體的模擬以及量測,證實此元件架構的崩潰電壓(Breakdown Voltage,VBD)可達18伏特以上,特徵導通阻值(Specific on-resistance,RON,SP)約為8.8mΩ∙mm2,且由統計分佈,藉由計算元件的特性變化範圍可知其變化誤差為13%以下,而此元件在125˚C下烘烤1000小時後,其特性變化亦在誤差值之內。


    In recent years, the improvement of power electronics and power devices is one of keys when the energy issues become more important. The cost down and the tradeoff between breakdown voltage and on-resistance have always been major concerns in designing power devices. Many studies have proposed their structure only needs few masks. However, it is still special process which needs wire bonding to connect the power device and main circuit. It is a limit for cost down.
    In this thesis, a novel 20V-class device with CMOS logic compatible process is proposed which called Contact Gate MOSFET (CGMOS). Since the device does not need the mask of drift region and wire bonding, it could be cost down substantially. By T-CAD simulation and measurement, the newly designed device has breakdown voltage up to 18 volt and 8.8mΩ∙mm2 specific on-resistance. From statistical distribution, the stability of device is up to 87%. And no characteristic variation can be observed after long term temperature stress at 125˚C for 1000 hours.

    摘要 Abstract 致謝 內文目錄 附圖目錄 表格目錄 第一章 序論 1.1 研究動機 1.2 章節介紹 第二章 操作原理與發展回顧 2.1 元件操作原理 2.1.1 導通與耐壓機制 2.1.2 崩潰機制 2.2 20伏特等級元件回顧 2.3 總結 第三章 元件設計與模擬 3.1 CGMOS元件設計概念 3.2 CGMOS元件模擬 3.2.1 崩潰特性模擬 3.2.2 導通特性模擬 3.3 CGMOS特性探討 3.4 總結 第四章 元件的製作與量測 4.1 元件製程流程 4.2 CGMOS特性量測與探討 4.2.1 崩潰特性量測 4.2.2 導通特性量測 4.3 元件可靠度分析 4.4 總結 第五章 結論 參考文獻

    [1]B.Murari, F.Bertotti, and G.A.Vignola, “Smart Power ICs”
    [2]T. Kobayashi, H. Abe, Y. Niimura, T. Yamada, A. Kurosaki, T. Hosen, and T. Fujihira, “High-Voltage Power MOSFETs Reached Almost to the Silicon Limit”, Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 435-438. 2001.
    [3]B.J. Baliga, “Power Semiconductor Devices”
    [4]Abraham Yoo, Yasuhiko Onish, Edward Xu, and Wai Tung Ng, “A Low-Voltage Lateral SJ-FINFET With Deep-Trench p-Drift Region”, IEEE Electron Device Lett., vol.30, pp. 858-860, 2009.
    [5]Lingpeng Guan, Johnny K. O. Sin*, Zhibin Xiong, and Haitao Liu, ” A Novel Drift Region Self-Aligned SOI Power MOSFET Using a Partial Exposure Technique”, Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 159-162. 2005.
    [6]Jacky C. W. Ng, Johnny K. O. Sin and Lingpeng Guan, “A Novel Sub-20V Power MOSFET with Improved On-Resistance and Threshold Variation”, Proc. Intl. Symp. Power Semiconductor Devices & Integrated Circuits, pp. 91-94. 2008.
    [7]Wang Cuixia, Cen Feng, Kan Hongjin, Yu Youling, “Low-FOM planar MOSFET”, in ICIMA, pp. 460-463. 2010.

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