應用於鎖相迴路之高頻除頻器｜國立清華大學博碩士論文庫

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研究生：	林宏育 Hong-Yu Lin
論文名稱：	應用於鎖相迴路之高頻除頻器 High-Speed Frequency Divider for Phase-Locked Loop Applications
指導教授：	徐碩鴻 Shuo-Hung Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	中文
論文頁數：	87
中文關鍵詞：	除頻器、注入鎖定式除頻器、主動電感、頻寬擴張技巧、鎖相迴路
外文關鍵詞：	frequency divider, injection locked frequency divider, active inductor, bandwidth extension, phase locked loop
相關次數：	點閱：3 下載：0
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摘要

現今通訊對於高資料量和高資料傳輸速度的要求，迫使通訊系統的操作頻率往更高頻的方向邁進。因此將來的通訊系統將會操作於較高的頻率區間，這代表通訊系統裡，某一些電路方塊將工作於相當高的頻率下。除頻器對於各種通訊系統而言，是不可或缺的電路方塊，尤其是鎖相迴路，除頻器降低輸入訊號的頻率，讓此較低頻的訊號，能夠讓其他系統使用。對於越來越高操作頻率的通訊系統而言，高頻除頻器顯的重要且必須的。
本報告最重要的核心重點，在於如何設計不同的高頻除頻器，並且使用標準的CMOS製程。首先介紹鎖相迴路的基本原理，在此將會詳細介紹除頻器，在鎖相迴路裡所扮演的角色，以及使用高頻除頻器所帶來的好處。此報告將實現一個完全積體電路化，且使用標準0.18-□m CMOS製程的除頻器，此除頻器操作頻率高於20GHz ，並且能夠提供給 Local Multipoint Distribution System 所使用。所提出的除頻器是由類比電路、和數位電路所構成的，且在頻率範圍 18.8GHz ~ 23.2GHz 內，此除頻器能夠將輸入頻率正確的除以四。
再者，一個具有主動電感，且使用標準CMOS製程的除頻器被實現，此提出的除頻器使用主動電感，取代傳統被動電感，利用主動電感面積小的優點，大幅縮小除頻器所需要的晶片面積。且使用source degeneration的方法，提升除頻器的操作頻率。從量測結果可知，此除頻器在頻率範圍5.4GHz ~ 6.4GHz內，都能將輸入頻率正確的除以2，於其他電路相同架構相比之下，本次工作擁有較小的晶片面積。最後介紹一個具有迴授電阻的除頻器，此除頻器利用迴授電阻，大幅提升除頻器的操作頻率，從模擬結果可知，所提出的除頻器能夠正確工作在12GHz ~ 20GHz，且與其他除頻器相比而言，所提出的除頻器，在相同操作頻率下，具有較小的晶片面積。

ABSTRACT

The demand of the high data capacity and high transmitting rate makes the operation frequency of the communication system increases rapidly. The frequency divider, typically used for phase-locked loop, plays an important role in a communication system. The frequency divider reduces the high frequency to low frequency for certain application.
The main focus of this work is to design various frequency dividers based on a standard CMOS technology. The basic theory of the Phase Locked Loop (PLL) is introduced in the beginning, which illustrates the importance of a frequency divider, and the advantage of using high frequency divider for PLL. A fully integrated frequency divider is implemented by a 0.18-□m CMOS technology and demonstrates an operation frequency up to 20GHz for Local Multipoint Distribution System (LMDS) applications. The proposed frequency divider consists of both analog circuit and digital circuit with a function of divided by 4 in the frequency range from18.8GHz ~ 23.2GHz.
Second, a frequency divider with active inductor is implemented in CMOS technology. The proposed frequency divider replaces the passive spiral inductor with active inductor to reduce the required chip area significantly. The methodology of source degeneration is used to increase the operation frequency. From measurement results, the proposed frequency divider has the function of divided by 2 in the frequency range from 5.4GHz ~ 6.4GHz. Compared with other works, this work has the smaller chip area under the same circuit topology.
A frequency divider with feedback resistor is designed, which employs a feedback resistor to increase the operation frequency. From simulation results, the feedback resistor can increase operation frequency effectively. The proposed frequency divider can operate in the frequency range from 12GHz to 20GHz. Compared with other works, this work has the smaller chip area under the same operation frequency.

Table of Contents

Abstract                            I
Table of Contents                       IV
Figure Captions                      VII
Table Captions                       XI
Chapter1 Introduction
    1.1 Motivation                    1
Chapter2 Theory of PLL
    2.1 Introduction to PLL                  3
    2.2 Basic Principle of PLL                5
    2.3 Important Specification of Frequency Synthesizer                        7
    2.3.1 Introduction                    7
    2.3.2 Phase Noise                    7
    2.3.3 The Effect of Phase Noise in Communication System                                      9
    2.3.4 The Effect of Spurs in Communication System                                     10
    2.3.5 Locking Time of Frequency Synthesizer       11
    2.4 Phase Frequency Detectors           13
    2.4.1 Phase Detector               13
    2.4.2 Phase Frequency Detector           14
    2.5 Charge Pump                   17
    2.5.1 Operation Principle of Charge Pump and PFD                                     17
    2.6 Loop Filter                   18
    2.7 Voltage Controlled Oscillator           19
    2.7.1 The Concept of Oscillator           19
    2.7.2 The Principle of LC Tank Oscillator       20
    2.7.3 LC Tank Voltage Controlled Oscillator       21
    2.8 Frequency Divider               25
    2.9 The Design Methodology of PLL           28
    2.9.1 The Linear Mathematical Model of PLL       28
    2.9.2 The Designed Methodology of Third Order Phase Locked Loop       29
    2.10 Conclusion                   32
Chapter3 A Wide Locking-Range Frequency Divider for LMDS Applications
    3.1 Introduction of LMDS               33
    3.2 The Principle of Analog Frequency Divider       34
    3.3 The Injection-Locked Frequency Divider       36
    3.3.1 The Principle of Injection-Locked Frequency Divider                                          36
    3.3.2 The Design Methodology of Injection-Locked Frequency Divider                                         40
    3.4 The Second-Stage Frequency Divider       42
    3.4.1 Introduction to Digital Frequency Divider                                42
    3.4.2 The Operation Principle of Digital Frequency Divider                                 43
    3.5 The Wide Locking Range Frequency Divider for LMDS Applications
    3.5.1 The Design Methodology of Wide Locking    Range Frequency Dividerfor LMDS Applications           45
    3.5.2 The Simulation Results           46
    3.6 The Measurement Results               52
    3.7 Conclusion                   55
Chapter 4 Two Improved Frequency Dividers
4.1 Frequency Divider with Active Inductor
         4.1.1 Introduction                   56
    4.2 The Theory of Active Inductor           56
    4.3 Source Degeneration                        59
    4.4 The Simulation Results             64
    4.5 The Measurement Results               69
    4.6 Conclusion                   72
4.7 Frequency Divider with Feedback Resistor
    4.7.1 Introduction                           73
    4.8 Bandwidth Extension               73
    4.9 The Simulation Results               77
    4.10 Conclusion                   82
Chapter 5 Conclusion                   83
References                       85

Figure Captions

Figure 2.1 Architecture of a homodyne receiver.    4
Figure 2.2 Block diagram of charge-pump PLL.        6
Figure 2.3 (a) ideal output spectrum of an oscillator.(b) actual output spectrum of an oscillator.          8
Figure 2.4 The effect of Phase Noise in receiver.         9
Figure 2.5 The effect of spurs in receiver.           11
Fig. 2.6 The locking transient of frequency synthesizer.                                12
Fig. 2.7 The ideal characteristic of Phase Detector.                                    13
Fig. 2.8 The state diagram of Phase Frequency Detector.                                14
Fig. 2.9 The conventional circuit topology of Phase Frequency Detector.                             15
Fig. 2.10 The time diagram of Phase Frequency Detector.                                16
Fig. 2.11 The characteristic of Phase Frequency Detector.                                16
Fig. 2.12 The circuit topology of PFD and CP.           18
Fig. 2.13 The negative-feedback system.           19
Fig. 2.14. (a) LC-tank without negative resistor (b) LC-tank with negative resistor
-Rp.                           21
Fig. 2.15. The ideal characteristic of Voltage Controlled Oscillator.                                 22
Fig. 2.16 The cross-couple pair.               23
Fig. 2.17 The C-V curve of MOS capacitor.           23
Fig. 2.18 (a) A conventional differential LC-tank Voltage Controlled Oscillator
(b) A complementary differential LC-tank Voltage Controlled Oscillator.                                      24
Fig. 2.19 The Pulse Swallow frequency divider.       26
Fig. 2.20 The frequency synthesizer block diagram with /2 frequency divider.                                           27
Fig. 2.21 The linear model of Phase Locked Loop.       29
Fig. 2.22 The second order Loop Filter.           30
Fig. 2.23 The wanted Bode plot of third order Phase Locked Loop.                                          30
Fig. 3.1 The Regenerative frequency divider.           34
Fig. 3.2 The Parametric frequency divider.           35
Fig. 3.3 (a) The linear model of a free-running LC oscillator.
(b) The mathematical model of an Injection-Locked Frequency Divider.                                               36
Fig. 3.4 The schematic of Injection-Locked Frequency Divider.                                     40
Fig. 3.5 The schematic of second stage.           42
Fig. 3.6 The time diagram of digital frequency divider.   43
Fig. 3.7 The total schematic of wide locking range frequency divider for LMDS applications.           45
Fig. 3.8 The output frequency of first stage is 9.4GHz.                           47
Fig. 3.9 The output frequency of second stage is 4.7GHz.                                47
Fig. 3.10 The output signal of second stage (time domain).                                48
Fig. 3.11 The output frequency of first stage is 12GHz.                           48
Fig. 3.12 The output frequency of second stage is 6GHz.                                49
Fig. 3.13 The output signal of second stage (time domain).                                49
Fig. 3.14 The output frequency of first stage is 12.5GHz.                                50
Fig. 3.15 The output frequency of second stage is 6.25GHz.                                50
Fig. 3.16 The output signal of second stage (time domain).                                                  51
Fig. 3.17 The photograph of wide locking range frequency divider for LMDS applications.               52
Fig. 3.18 The output frequency is 4.7GHz, when input frequency is 18.8GHz.                                  53
Fig. 3.19 The output frequency is 5.0GHz, when input frequency is 20GHz.                                  53
Fig. 3.20 The output frequency is 5.8GHz, when input frequency is 23.2GHz.                                  54
Fig. 3.21 The phase noise of output frequency is 4.7GHz.  54
Fig. 4.1 The equivalent model of Gyrator.           57
Fig. 4.2 The circuit schematic of active inductor.       57
Fig. 4.3 The input impedance of active inductor vs. frequency.                            59
Fig. 4.4 (a) The cross-couple pair with source degeneration. (b) The equivalent model of cross-couple pair with source degeneration.                   60
Fig. 4.5. The circuit schematic of frequency divider with active inductor.                                      64
Fig. 4.6 The output frequency is 3.8GHz, when input frequency is 7.6GHz(frequency domain).                65
Fig. 4.7 The output signal is 3.8GHz, when input signal is 7.6GHz(time domain).                   65
Fig. 4.8 The output frequency is 5GHz, when input frequency is 10GHz(frequency domain).                   66
Fig. 4.9 The output signal is 5GHz, when the input signal is 10GHz(time domain).                   66
Fig. 4.10 The output frequency is 5.1GHz, when input frequency is 10.2GHz (frequency domain).           67
Fig. 4.11 The output signal is 5.1GHz, when the input signal is 10.2GHz(time domain).               67
Fig. 4.12 The die photograph of the frequency divider with active inductor.                                      69
Fig. 4.13 The output frequency is 2.7GHz, when input frequency is 5.4GHz.                                  70
Fig. 4.14 The output frequency is 2.8GHz, when input frequency is 5.6GHz.                                  70
Fig. 4.15 The output frequency is 3.2GHz, when input frequency is 6.4GHz.                                  71
Fig. 4.16 The phase noise which carrier frequency is 1GHz is -123.2 dBc/Hz at 1MHz offset.               71
Fig. 4.17 (a) single stage of frequency divider with feedback resistor (b) equivalent small signal model (c) equivalent small signal model with Miller’s theorem.       75
Fig. 4.18 The circuit schematic of the frequency divider with feedback resistor.                                  75
Fig. 4.19 (a) The free-running frequency of the proposed frequency divider without feedback resistor (b) The free-running frequency of the proposed frequency divider with feedback resistor.                       76
Fig. 4.20 The output frequency is 6GHz, when the input frequency is 12GHz (frequency domain).           77
Fig. 4.21 The output signal is 6GHz, when input signal is 12GHz(time domain).                   78
Fig. 4.22 The output frequency is 8GHz, when the input frequency is 16GHz (frequency domain).           78
Fig. 4.23 The output signal is 8GHz, when input signal is 16GHz(time domain).                   79
Fig. 4.24 The output frequency is 10GHz, when the input frequency is 20GHz (frequency domain).           79
Fig. 4.25 The output signal is 10GHz, when input signal is 20GHz(time domain).                   80
Fig. 4.26 The layout of the frequency divider with feedback resistor.                                          81

Table Captions

Table I Compare with other works.               51
Table II Compare with other works.                                       68
Table III Compare with other works.                                       81

                                

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