適用於多重輸入輸出都會型寬頻無線網路通訊系統之基頻處理器矽智財設計

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研究生：	尤欣怡 Hsin-Yi Yu
論文名稱：	適用於多重輸入輸出都會型寬頻無線網路通訊系統之基頻處理器矽智財設計 An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	63
中文關鍵詞：	多輸入多輸出、正交分頻多工存取、無線都會網路、元件可程式邏輯閘陣列
外文關鍵詞：	MIMO, OFDMA, WIMAX, FPGA
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　近年來，正交分頻多工存取已廣泛為人所探討，並被視為未來第四代無線通訊系統技術，正交分頻多工存取傳輸系統同樣遇到在正交分頻多工傳輸中所遭受的問題，特別是在頻率漂移的同步和通道的不理想效應。上傳通訊系統接收機更面臨多個載波頻率漂移和多路徑通道的效應，當引進多輸入多輸出天線技術以提升多人使用時的傳輸速率時，有效地解決正交分頻多工存取系統在頻率同步和多路徑通道干擾成為一個極具挑戰性的問題。

　　在本論文中主要是探討設計一個根基於IEEE 802.16e的正交分頻多工存取的上傳接收機，包含系統介紹、電路設計、元件可程式邏輯閘陣列板及SoC驗證平台。所提出的接收機包含一個根基於不同載波間干擾消除的載波頻率漂移估測器、不同載波間干擾消除器、通道估測器、多輸入多輸出偵測器和一般的正交分頻多工存取技術基頻模組。系統操作在兩個模式，第一個模式是估測各個使用者的載波頻率漂移大小，此模式藉由線性內插及外插估測通道資訊的輔助，並使用二元搜尋方式來估測載波頻率漂移的方式，如此可降低硬體複雜度並仍然維持估測精準度，在估測完各個使用者的載波頻率漂移大小後則會進入資料補償模式。

　　本論文所提出低複雜度架構相較於傳統的架構可以節省80%的邏輯閘數，採用模組化的設計加速驗證過程，除了已經經過元件可程式邏輯閘陣列板驗證成功，目前可實際在SoC驗證平台傳送多媒體資料。

Recently, orthogonal frequency division multiple access (OFDMA) systems have been regarded as next generation communication technique. OFDMA systems suffer the same problems as orthogonal frequency division multiplexin (OFDM) communication, especially in frequency synchronization and channel impairment. An uplink OFDMA receiver faces problems of multiple frequency offsets and multipath channels in an OFDM symbol because of multiuser transmission. Therefore, a base station (BS) design becomes a more challenging task. Especially when multi-input multi-output (MIMO) technology is applied to OFDMA communication to improve detection quality or to increase data rate, synchronization and channel estimation problems become more complicated.
In this thesis, a prototype of OFDMA uplink transceiver design based on IEEE 802.16e standard is proposed and implemented. The proposed transceiver consists of an inter-carrier interference/ multiple-access interference (ICI/MAI) canceller, an ICI-cancellation-based carrier frequency offset (CFO) estimator, a channel estimator, a MIMO detector and a general OFDMA baseband engine. The proposed architecture is aim to estimate the CFO with low cost but high precision based on ICI cancelation and with the help of channel estimation by binary search method. Linear interpolation/extrapolation and coefficient approximation technique are applied in channel estimation for reducing hardware complexity but still with high performance. The proposed architecture has 342 gate-count saving compared to conventional one and is implemented in field-programmable gate array (FPGA) board and integrated in
SoC platform.

Contents
Introduction 1
1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 OFDM and OFDMA . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
System Description 7
1 Introduction of IEEE 802.16e Standard . . . . . . . . . . . . . . . . . . . . . 7
1.1 Symbol Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Subcarrier Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 System Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Architecture Design 13
1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Proposed MIMO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 System Performance and Word-length Determination . . . . . . . . . . . . . 23
Logic Design 29
1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 CFO Estimation Mode . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2 Data Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . 31
2 Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 CP Remover, FFT and Subchannel De-assignment . . . . . . . . . . 31
2.2 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3 ICI Cancelation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5 Noise Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6 MIMO Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7 De-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . . 42
FPGA Emulation and SoC Integration 47
1 Verification Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1 FPGA Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.4 Emulation Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.5 FPGA Emulation Result . . . . . . . . . . . . . . . . . . . . . . . . 52
3 ARM Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Conclusions 59
1 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

                                

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