鍺基板作為下一代前瞻的半導體材料，擁有比矽還要高的遷移率，可以使元件的功耗變低、使操作效率更好，但是製作二氧化鍺的時候會遇到許多問題，例如說在高溫下二氧化鍺會脫附成品質較差的氧化鍺，使得Ge/GeO2接面製程不容易維持良好的品質等。因此，適當的介面層處理是實現高性能金氧半鍺電晶體的關鍵，透過不同溫度的先、後氧化以及電漿製程處理來改善閘極介面品質，本論文研究以鍺基板nMOSFET為主題，探討不同閘極介面製程與汲極、源極的PN接面製程優化，並探討其電特性。
首先，使用氫電漿作為蝕刻的製程，利用H2 plasma與GeO2反應產生氣體的GeH4與H2O，使鍺基板的氧化層減少，探討不同秒數的蝕刻對熱氧化二氧化鍺介面的電性影響。實驗結果顯示，使用熱氧化GeO2搭配5秒氫處理，應用HfN/ZrO2 作為閘極介電層的元件，相較於未處理的元件可以使EOT由7.2 Å減少到6.3Å，同時介面產生的氧空缺最少，並有最佳的可靠度與均勻性。
第二部分是利用先沉積介電層、後氧化的製程，期望氧化層在高介電係數材料與鍺基板之間可以形成二氧化鍺介面層，觀察不同材料在後氧化製程對電容器的電性影響。實驗結果發現，後氧化製程的電容特性並沒有比氫電漿製程的好，但由不同材料的沉積結果可以發現，HfNx作為介電材料可以使電容特性有比較良好的表現。接著，再延伸探討不同溫度的先氧化製程對電容的特性影響，找到了p型鍺基板電容元件下，二氧化鍺的最佳形成溫度為350°C，可以使元件的均勻度與電性達到最佳。
最後一個部分，則是先利用不同方法的沉積製程製作佈植前的氧化犧牲層和隔離層來製作n+/p接面，希望能減少佈植缺陷與表面漏電流。再把前兩章所研究到的最佳化閘極使用於電晶體，搭配最佳的閘極參數與n+/p接面參數來製作金氧半鍺電晶體，探討不同的介面鈍化製程對電晶體的影響，研究結果顯示氨氣電漿的使用可以讓元件的電流開關比達到最高2.75個order、次臨界擺幅可以達到155mV/dec、且元件閘極漏電流在Vg=Vfb-1V時抑制到2.55×10-5A/cm2。

Germanium is regarded as one of promising semiconductor materials for next generation because of the higher carrier mobility than silicon, which can achieve high device performance. However, many problems of device degradation may be encountered. For example, GeO2 is easily desorbed at high temperature process, making it difficult to maintain good quality at Ge/GeO2 interface. Therefore, a suitable interface engineering is the key to realize high performance Ge MOSFET. In this thesis, Ge substrate/gate oxide interface is improved by pre-oxidation and post oxidation at suitable temperature, and various plasma passivation processes. The process optimization of n+/p junction is also studied. Finally, Ge n-MOSFETs are fabricated to investigate electrical characteristic.
First, a hydrogen plasma is used as oxide etching process. GeO2 is scavenged by reacting GeO2 with H2 plasma before high-κ gate dielectric deposition. Ge MOS capacitor with a H2 plasma treatment for 5 seconds shows the fewest oxygen vacancies and the best reliability and uniformity. Moreover, the equivalent oxide thickness can be reduced, compared to 7.3Å of sample without a H2 plasma treatment.
Second, effects of high-κ interfacial layers with post oxidation on electrical characteristic of Ge p-MOS devices are investigated. By using post oxidation, GeO2 interfacial layer would be formed at high-κ material and Ge substrate interface. The experimental results show that the electrical characteristics of device with post-oxidation are worse than those with a thermal grown GeO2 and hydrogen plasma process. It is also found that samples with HfNx interfacial layer show fewer border traps in gate dielectric. Then, GeO2 interfacial layer grown at different temperatures are investigated. It is observed that device with GeO2 grown at 350°C shows the best electrical characteristics and uniformity.
Third, in order to reduce the ion implantation-induced damage and surface leakage current, the n+/p junctions are passivated with thermal grown GeO2 sacrificial layer and the isolation layer. Finally, the effects of passivation process on Ge n-MOSFET with GeO2/HfNx/ZrO2 gate stack are studied. Device with NH3 plasma treatment shows the highest on-off ratio of 2.75 orders, small subthreshold swing of 155mV/decade, and small gate leakage current of 2.55×10-5A/cm2 at Vg=Vfb-1V.

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