由於浮動式閘極快閃記憶體無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體式取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽做為電荷儲存層的結構，在發展到次微米以下時就無法再以降低穿隧氧化層厚度的方式來提升元件操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作機制。而在通道介面處磊晶一層矽化鍺或純鍺，藉由能帶工程提升操作載子的能量，希望藉此材料的應用達到較高的元件操作效率。
比較矽化鍺、純鍺通道中，藉由調變不同的單晶矽覆蓋層厚度，改善矽化鍺、純鍺通道與穿隧氧化層之間的界面特性，探討對於TAHOS元件的效率影響。 比較矽化鍺、純鍺通道中，藉由調變不同的溫度，觀察鍺原子受到溫度的影響所對元件產生的效應，探討對於TAHOS元件的效率影響。利用不同的方法達到高濃度矽化鍺或純鍺結晶層，探討不同方法對於高濃度矽化鍺與純鍺結晶層的優缺點。
而經由實驗結果發現，單晶矽覆蓋層的選擇是非常重要的，些微的厚度都會影響寫入、抹除與電荷保持的特性。不同的退火溫度會直影響元件的寫入、抹除與電荷保持的特性(在低鍺含量的矽化鍺通道元件中，不易觀察到)。利用乾式氧化達成高鍺含量的矽化鍺薄膜其結晶狀況雖佳，但是表面粗糙度很差，不適合使用其結果製作元件，而使用超晶格所製作出來的純鍺薄膜，則擁有良好的結晶狀況與良好的表面粗糙度，是未來做為純鍺通道的良好方法。

Abstract
Charge-trapping (CT) flash is regarded as one of the most promising nonvolatile memory devices. Some approaches were proposed to further enhance the operation properties of CT flash devices by stacked high-k charge-trapping layer , stacked tunneling oxides with thicker physic thickness , metal gate with high work function, and SiGe buried channel(small band gap) .
SiGe and Ge buried channel with different annealing temperature and various thicknesses of Si-cap layer on operation characteristics of charge-trapping (CT) flash devices were studied in this work. And We use different method to formation of high concentration SiGe layer or crystalline Ge layer.
We can have 5 Conclusions, 1. Programming and erasing speeds of all samples with SiGe buried channel are faster than control sample.2. The thickness of Si-cap would affect the properties of programming and retention obviously.3. For deuces with pure Ge channel , lower annealing temperature should be better for the electrical properties of devices.4. The roughness of condensed SiGe layer would be a serious issue for the device fabrication.5. Good crystalline structure and low roughness SL layer would be a good buffer layer for the growth of crystalline Ge layer.

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