摘 要
由於快閃記憶體的讀寫均是藉由熱載子傳輸來達到電荷儲存和抹去的目的。因此在執行這些動作的同時，就非常有可能對於浮動閘極氧化層以及界面產生局部性的損害。而這些損害會使得記憶體元件電特性下降，並對於可靠度產生嚴重影響。因此為了能夠深入了解記憶體損害的程度以及局部熱載子對元件的影響。我們根據電荷汲引量測發展出一套直接萃取氧化層電荷和界面陷阱側向分佈的技術。由於此技術可直接從量測到的電荷汲引曲線獲得所要結果，並不需要繁雜的數值模擬。已然成為研究熱載子損傷最好的量測工具之一。 雖然

此方法在理論上好像相當容易，但是在實際上卻有一個相當難克服且不容易執行的步驟（氧化層電荷中和的步驟）。也由於此步驟並不容易執行且確定，常常使得所求得的Not和Nit分佈帶著相當程度的誤差，使之實驗失去了應有的準確性。為了要去改善此方法所造成的缺失，在本論文中我們提供了二種針對中和步驟改善的方法，其一為二階段中和步驟，其二為電荷汲引曲線數值修正。而這些改善的方法對於提升電荷汲引量測技術的準確性有著相當程度的助益。在本研究的最後，我們選取了8051微控制器（Micro-controller）和SRAM 靜態隨機存取記憶體來進行輻射總劑量測試以及低劑量效應測試，用以作為太空元件抗輻射影響評估可靠性的指標。

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