低密度奇偶檢查碼(LDPC codes)的錯誤平層(Error-floors)是重大的障礙當應用在許多需要極低錯誤率的通訊系統和儲存設備。它被歸咎於低密度奇偶檢查碼的Tanner圖有特殊的結構，那經常會困住訊息傳遞解碼演算法(message-passing decoding lgorithm)，而且阻止解碼的結果收斂到傳輸的碼字(codewoed)。我們提出一個技術可以降低二位元低密度奇偶檢查碼和非二位元低密度奇偶檢查碼(Non-binary LDPC)的錯誤平層。根據解碼失敗的結果，一些不可靠的變數節點(variable-nodes)可以在前一次疊代中被指認出來。提出的技術是強制給一個極端值到一個不可靠的變數節點然後重新執行解碼的程序。依據可靠度強制給值(reliability-based forcing)的技術可以使解碼器避免錯誤的事件，而且只伴隨適當的複雜度。我們也實作這個技術在硬體模擬平台在上面。此外，(3, 12)-regular 32-ary (372, 286) 和(3, 12)-regular 16-ary (180, 141) 非二位元類循環低密度奇偶檢查碼(QC-LDPC codes)被展示在可加性高斯白雜訊(AWGN)通道環境中藉由被設計出的多重場(multi-eld (Galois eld))解碼器使用FPGA(field-programmable gate array)平台。這個平台確實加速了非二位元低密度奇偶檢查碼的模擬。模擬的結果顯示提出來的技術有效地降低了錯誤平層好幾
個層級。

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