同時考量電壓源下降和串音干擾的時序分析方法

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研究生：	包洵瑋 Hsun-Wei Pao
論文名稱：	同時考量電壓源下降和串音干擾的時序分析方法 Timing Analysis Considering Simultaneous IR drop and Crosstalk Noises
指導教授：	張世杰 Shih-Chieh Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	36
中文關鍵詞：	電壓源下降、串音干擾、時序分析
外文關鍵詞：	IR drop, crosstalk, timing analysis
相關次數：	點閱：2 下載：0
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在先進製程下，訊號完整性的雜訊變的越來越嚴重，其中最常見的兩種雜訊是電壓源下降和串音干擾。這兩種雜訊皆會造成電路的延遲增加，此外，也有可能造成使得邏輯閘的功能失靈而導致錯誤的輸出。再者，電壓源下降和串音干擾將會交互影響，使得考慮雜訊的時序分析方法成為關鍵的課題。傳統的時序分析方法是將電壓源下降所產生的延遲與串音干擾所產生的延遲疊加。在這篇論文裡，經由實驗，我們發現兩者結合所產生之延遲效應遠比個別考慮之後疊加更為複雜，尤其在九十奈米以下的製程技術下，這樣的現象更為顯著，平均而言，雜訊結合效應比疊加結果高出8%。因此，為了準確計算因電壓源下降和串音干擾雜訊產生的延遲，我們首先建立了一個三維的標準元件庫以及使用回歸分析方法，來儲存單一邏輯閘在電壓源供給、輸入電壓及輸出電容大小不同時的延遲，再使用切割訊號轉換區間的概念配合查表法來估計電壓降及串音干擾的雜訊及其同時發生時的結合效應所造成之延遲。同時，我們也提出一個迴圈式的方法反覆地處理兩者交互影響下所產生的雜訊。執行速度上，我們的靜態時序分析方法比SPICE模擬平均快了一千倍以上，實驗結果證實切割訊號轉換區間的概念可以大幅增加準確度，因此我們的論文非常具有發展性。

The noise problem becomes a critical issue in the advanced technology when IR drop and crosstalk noises occur simultaneously. Traditionally, timing analysis superposes induced delays by the IR drop noise and also by the crosstalk noise. In this paper, we observe that the combined effect of both noises is much larger than the superposition of individual noise induced delays. To accurately compute the noise induced delay, we use the concept of the sliced switching window to estimate the IR drop noise and the crosstalk noise. We also propose an iterative methodology to consider the combined effect of IR drop and crosstalk noises. Our experimental results are very promising.

List of Contents:
Abstract    1
Contents    2
List of Figures    3
List of Tables    4
Chapter 1 Introduction    5
Chapter 2 Gate Delay Model for the Combined Effect    10
Chapter 3 Noise delay by Sliced Switching Window    14
3.1. Sliced Switching Window    15
3.2. IR drop Noise delay    18
3.3. Combined Noise delay    21
Chapter 4 Methodology    24
Chapter 5 Experimental Results    27
Chapter 6 Conclusions    34
References    35

List of Figures:
Figure 1: A circuit with the IR drop and crosstalk noises    6
Figure 2: An inverter's rising delay    11
Figure 3: Effective capacitance model    12
Figure 4: A gate's delay computation for the combined effect    13
Figure 5: Two kinds of switching windows    16
Figure 6: Noise delay computation with the IR drop noise    18
Figure 7: Noise delay computation with the combined noise of the IR drop andcrosstalk noises    21
Figure 8: Combined noise-aware timing analysis methodology    25
Figure 9: Our detail experimental flow    28
Figure 10: IR drop waveform of C3540    32



List of Tables:
Table 1: Noise delays when considering different kinds of noises    6
Table 2: The comparison between the total noise delays and the combined noisedelays    30

                                

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