為了減低電路上的功率消耗，許多研究展示在某些情況之下可以利用關閉時脈訊號並且不改變電路的功能來降低電路的運算，以達到節省功效的目的。我們觀察到當在做時脈閘控時，組合電路和閘控電路是有關連性的，並且可以利用這個關聯性來簡化循序電路。在我們的論文中，在時脈訊號被適當的閘控下，我們展示了組合電路可以只是個正反器。我們利用時脈閘控電路和組合電路之間的彈性，提出了一個啟發式演算法來同時簡化組合電路和時脈閘控電路並且來對循序電路做最佳化，另外，因為我們的方法不同於傳統的方法，在某些電路上我們得到了非常好的結果。

To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the clock-gating conditions and the next-state function of a Flip-Flop (FF) are correlated and can be used for sequential optimization. We show that the implementation of the next-state function of any FF can be just an inverter if the clock signal is appropriately gated. By exploiting the flexibility between the clock-gating conditions and the next- state function, we propose an iterative optimization technique to minimize the overall timing. Because our methodology is totally different from the traditional ones, we obtain extraordinarily good timing results on certain circuits.

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