此論文設計、模擬與分析一寬頻AB類功率放大器，並使用台積電所提供之六十五奈米CMOS製程下線，論文共分五章，前兩章說明功率放大器的應用以及相關設計理論，接著為此功率放大器的設計流程、電路模擬和結果分析，完整的電路包含射頻發射器的輸入緩衝級、功率級以及連接至輸出端的平衡-不平衡變壓器。
主要研究的寬頻AB類功率放大器將應用於短脈衝射頻發射器，兩個相位差一百八十度之時脈訊號經過時脈緩衝開關後輸出至功率放大器，此時脈訊號即為功率放大器之操作頻率，經過時脈緩衝開關後，訊號會成為寬度一奈秒、週期一百奈秒之短脈衝，而後經過功率放大器將阻抗轉換為五十歐姆的輸出阻抗，並接至天線量測。發射器電源電壓為1.0V，啟動時的功率消耗約為33mW，而功率放大器在主操作頻率7.5GHz時輸出飽和功率達9dBm以上，輸入三階截止點為13dBm，功率附加效率則為25％，可操作頻寬由3.2GHz至8.6GHz，而此頻寬定義為三分貝之正向電壓增益衰減，且輸出反射係數需小於負六分貝，另外因應計劃需求，在主操作頻率7.5GHz附近將有最低的輸出反射係數，以避免量測用之印刷電路板上形成駐波進而影響輸出結果。

In this thesis, there is a wideband class-AB power amplifier (PA) had been designed, simulated, analyzed, and taped out with TSMC 65nm CMOS technology. The thesis is organized into five chapters. The first two chapters are the applications, related parameters, and design theories of the PA. The other chapters are about the design flow, circuit simulation and results analysis. The complete circuit is a radio-frequency transmitter, which includes an input buffer stage, a power stage, and a balance to unbalance transformer to connect with the output port.
The wideband class-AB PA is applied to the impulse radio-frequency transmitter. There will be two opposite phase clock signal through the switchable clock buffer to the PA, and the frequency of the clock signal will be the operation frequency of the PA. After the signal through the buffer, it will become a 1ns impulse with 100ns period, and then the PA will increase the power of the output signal for antenna measurements. The power supply of the transmitter is 1.0V, and the power consumption is about 33mW when turn on. The main operation frequency of the PA is 7.5GHz with 9dBm saturation power, 13dBm IIP3, and 25％ PAE. The operational bandwidth of the circuit is 3.2GHz to 8.6GHz. The definition of the bandwidth in this design is 3dB decrease of S21 and S22 should be smaller than -6dB to avoid the formation of standing wave on the PCB.

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