極化碼被證明是可達到向農容量的編碼，且被選為下世代行動通訊技術控制通道的參考編碼方式，近年來極化碼的研究變得非常熱門。當奇偶檢查碼幫助下的列表連續消去演算法被選為解碼演算法時有很好的錯誤更正性能。然而，循序解碼的特性與高硬體複雜度使其難以被應用於需要高可靠度與低延時的實際通訊系統中。因此，本文提出了包含後處理的以節點寬度為單位之列表連續消去極化碼解碼器，其中應用所提出的方法:包含不可靠位元的節點分析、有效率的節點處理、路徑量度正規化與後處理，以同時實踐高吞吐量與高可靠度，並改善硬體吞吐量面積比。所提出架構在TSMC 90nm 製程下，相較於先前文獻有較高的吞吐量面積比與錯誤更正能力。據我們所知，此硬體架構也為第一個實作包含後處理的列表連續消去解碼器。

Polar codes with list successive cancellation (LSC) decoding has been selected as the standard of fifth generation new radio (5G NR) control channel. In this work, we proposed a bit-reliability based node-wise (BRNW) CA-LSC decoder architecture. With the proposed bit-reliability based nodes (BRBN) and bit-reliability based nodes processing (BRNP) methods, the latency of our baseline architecture can be reduced around 37\%. Together with the proposed path metric normalization (PMN), the area efficiency of the baseline architecture improved almost 62\%. Even more, we also proposes post processing for bit-reliability based CA-LSC decoding which helps our decoder achieve better error rate performance under the same list size. The corresponding VLSI architecture implementation result is synthesized using the Taiwan Semiconductor Manufacture Company (TSMC) 90nm complementary metal oxide semiconductor (CMOS) process. Compared to other state-of-the-art architectures, our decoders achieves better area efficiency. To our knowledge, it is also the first hardware implementation of CA-LSC decoder with post processing, and it has almost 2.5 times area efficiency compared to the latest list size 32 decoder.

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