快閃記憶體（Flash Memory）是目前消費性電子產品中被廣泛使用的元件之一。在對於快閃記憶體可靠度以及讀取速度的考量之下，單層單元(Binary-Level Cell，BLC)和多層單元（Multi-Level Cell，MLC）快閃記憶體根據不同的需求被同時應用固態硬碟上面，這是一種可以得到高容量且高速儲存元件的較大經濟效益解決方案。然而由於快閃記憶體本身在一定可靠度下具有寫入/抹除（program/erase）次數的限制，如何隨著時間增長並維持良好的檔案完整性，便成了一項重要的議題。錯誤更正編碼（Error Correction Coding，ECC）是現今被拿來運用並且增加快閃記憶體的耐用性與可靠度。而BCH碼 (Bose-Chaudhuri-Hocquenghem codes) 以及漢明碼 (Hamming code) 是目前被廣泛應用在快閃記憶體上的錯誤更正編碼。

在這篇論文中，我們將焦點放在低密度偶校碼 (Low-Density Parity-Check codes, LDPC codes) 在快閃記憶體上的應用，這種錯誤更正編碼在訊息理論中被證實在一個受雜訊干擾的傳輸通道上能使檔案可靠傳輸的速度非常接近於最大理論值。我們針對低密度偶校碼搭配不同的解碼方式來討論將其應用在快閃記憶體上的可行性，之後我們就低密度偶校碼搭配和BCH碼同樣解碼層級的位元翻轉解碼器 (Bit-Flipping decoder)，並根據模擬以及估算的結果來比較這兩種錯誤更正碼應用在快閃記憶體上時所擁有的錯誤更正能力、解碼所需花費的時間、以及編碼解碼電路在記憶體電路中所占額外的面積。在一些假設前提下，根據比較的結果，發現低密度偶校碼搭配位元翻轉解碼器相較於BCH碼來說擁有較差的能力。儘管如此，還是可以朝著尋找低密度偶校碼搭配軟判決解碼方式 (soft-decision decoding) 應用在快閃記憶體上的方向上繼續研究其可能性。

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