對於各個模組提供不同的電壓，多重電壓分佈（multiple power domain）
是一個可以有效減少晶片能源消耗且保持其效能不變之技術。雖然已經有很多在
二維晶片下的多重電壓分佈之研究，但是在三維晶片下的多重電壓分佈之研究並
不多。在林碩士的論文中，基於陳博士所提出之堆疊穿透矽通道分發網路-STDN
（Stacked-TSV Distributed Network），林碩士提出一個將多重電壓分佈應用在
三維晶片上之演算法，他的演算法考慮了晶片之三維佈局（floorplan）、電壓壓
降（IR drop）、溫度、晶片面積等晶片屬性。在這篇論文中，我們提出一個電路
佈局後之能源最佳化（post-floorplanning power optimization）演算法，可
以進一步的減少電路佈局之設計的能源消耗。實驗結果顯示我們的演算法可以更
進一步的減少能源消耗、晶片面積及信號連線之繞線長度。

Multiple Power Domain (MPD) is a technique to optimize power and speed by providing multiple supply voltages to modules. Although there are many research on MPD in 2D IC, less research pay attention to MPD in 3D IC. In Lin’s thesis, an algorithm was applied to MPD in 3D IC to take into account issues such as 3D floorplan, IR drop, temperature, area, etc. based on an integrated architecture of stacked-TSV (Through-Silicon-Via) and power distributed network (STDN-Stacked TSV Distributed Network) proposed by Chen. In this thesis, we propose a post-floorplanning power optimization algorithm to further reduce power given a floorplan of MPD design produced by Lin’s algorithm. Experimental result show that our algorithm achieves more power reduction, less area of footprint and less total wirelength of signal interconnections.

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