隨著半導體技術的進步與系統晶片的整合，有越來越多的問題等待解決，在半導體記憶體方面也是同樣的面臨許多重大的問題：1. 因為記憶體的增加，測試時間與測試資料量也大幅的增加，而記憶體的量率則是相對的大幅減低；2. 記憶體的工作速度也隨著製程技術的進步而變快，所以延遲錯誤也出現於記憶體之中；3. 非揮發性記憶體的大幅使用開啟了許許多多新型記憶體的開發，而這些新型記憶體的測試卻尚待解決。這些問題限制了半導體記憶體的發展與應用。在本論文中，針對了這些記憶體的問題提供了相對的解決辦法。在記憶體增大的問題，開發出了以症狀識別為基礎的壓縮方法，此方法可以將大部分記憶體測試所產生的錯誤訊息壓縮至6%以下。為了減少測試與診斷的時間，本論也文提供的平行式測試與診斷的方法也可以將時間減少為原本的25%。而為了改進因面積增加而低落的記憶體量率，本論文提供了一套軟體RAISIN可以用來評估多餘記憶體的配置與相對演算法的效率；本論文也更進一步做了經濟面評估，探討多餘記憶體的加入與整體獲利的相對關係。為了解決操作速度而引起的延遲錯誤，本論文也針對兩種最常見的嵌入式記憶體（SRAM與DRAM）提供了延遲錯誤的測試演算法，此演算法並不會增加很多測試時間而且可以有效的偵測出記憶體的延遲錯誤。在非揮發性記憶體方面，本論文針對很有潛力的非揮發性記憶體MRAM做了詳細的缺陷分析，並建立的相關的錯誤模型，而且提供了測試演算法，此為磁性隨機存取記憶體測試提供了較系統性的測試方法。基於本論文提供的這些關於測試訊息壓縮、平行測試診斷、自我修復評估、延遲錯誤測試、磁性隨機存取記憶體測試的方法，可以有效的解決很多記憶體所面臨重要問題。

With the advent of deep submicron technology, system-on-chip
(SOC) design methodology, heterogeneous cores from different
sources can be integrated in a single chip that contains millions
of gates. However, the yield of such a large chip is usually too
low to be profitable, therefore, yield enhancement is an
important issue in SOC product development. Memory cores are
among most widely used cores of SOC integration, and an SOC that
contains hundreds of SRAM cores is not uncommon today. Memory
cores tend to dominate the SOC yield because they usually have a
high silicon density and large area characters. Consequently,
improving the yield of embedded memory is key in improving chip
yield. The many factors of yield enhancement can be divided into
some topics. First, memory diagnosis is needed, but the size of
test data increases exponentially as the size of memory
increases. Thus, fault pattern compression is needed to reduce
the size of the test data. Because of the large number of memory
cores in a chip, parallel testing and diagnosis is also needed to
reduce test time/cost. Secondly, after diagnosis of the memory
core, redundancy repair can improve the yield of memory. The
repair mechanism has many factors, such as redundancy analysis
(RA) algorithm selection, spare element types, and the number of
the spare elements. How to select these factors, which affect
the efficiency of RA performance and the benefit of the built-in
self-repair (BISR) design, needs to predict and evaluate. Timing
issues become more important with advance in process technology,
but they are difficult to test by built-in self-test mechanisms.
Additionally, non-volatile memory requirements have increased
recently, and there are many types of non-volatile memories. The
testing of the new memory types is also a new challenge.

In this paper, we present a few solutions for the important
memory issues. First, we propose a method for fail pattern
compression based on fail pattern identification, which can
compress data up to 6\%. The parallel diagnosis scheme proposed
in this paper reduces test/diagnosis time significantly: up to
25\% in the 512$\times$32 memory core. Additionally, an
efficient simulator RAISIN is proposed to evaluate the
performance and the benefit of the BISR circuit. The delay fault
behavior of embedded memory (including SRAM and DRAM) have been
analyzed and the efficient test algorithms are also proposed.
The proposed new test algorithms do not increase much time
complexity. For example, the test algorithm for SRAM is only
$10N+6k$ after integrated with March C$-$ test algorithm, which
only increases $6k$. Where $k$ is the word count in a row. The
magnetic random access memory (MRAM) is considered one of the
potential candidates that will replace the current memories (RAM,
EEPROM, and flash memory) in the future. In this work we
classify and analyze the MRAM defects and their behavior, and
propose its fault models. The circuit has been implemented and
fabricated with a new 0.18$\mu$m technology. The simulation
results regarding the correlation between the defects and
conventional fault models show that most defects are covered by
the stuck-at fault model. The test data based on the fabricated
chips show that the stuck-at faults do cover most of the defects
on the chips. However, from the experiment we also have
identified two new faults, i.e., the Multi-Victims fault and Kink
fault. The proposed approaches resolve the important memory
issues efficiently, including test data compression, parallel
testing, BISR design and evaluation, timing testing of embedded
memories, and MRAM fault modeling and testing.

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