近年來，隨著電子產品功能及效能的提升，對電子元件的的要求也隨之提高。電子封裝技術也由早期的DIP (Dual in-line Packaging)、SOP/TSOP (Small Outline Packaging / Thin Small Outline Packaging)、QFP/TQFP (Quad Flat Packaging / Thin Quad Flat Packaging)與BGA(Ball Grid Array)等發展至小體積且高密度的覆晶(Flip Chip, FC)、晶片尺寸封裝(Chip Scale Packaging, CSP)、晶圓級封裝(Wafer Level Packaging, WLP)、扇出型晶圓級晶片尺寸封裝(Fan-Out Wafer Level Chip Scale Packaging, FO-WLCSP)及系統式封裝(System-in-Packaging, SiP)等技術。
而許多研究顯示傳統晶圓級封裝在經熱循環測試後錫球接點處有可靠度的問題，因此許多學者提出想法改良。其中在錫球下方加入應力緩衝層吸收錫球之應力為一有效且被廣為使用的方法，但許多研究者發現應力緩衝層所產生的大變形反而使封裝中導線產生可靠度問題，因此本文主要針對所研究之FO-WLCSP結構探討導線經熱循環負載之可靠度。
以實驗方式進行研究較為耗時費力，所需金錢成本也較高，因此本文中採模擬的方式進行研究。為了確保模擬的可靠度，本文先建立了以Yew[17]等人所設計之FO-WLCSP結構為基礎的模型，並將模擬結果與其實驗數據相驗證得到了不錯的擬合度，確保了該模擬流程的正確性。
針對本研究FO-WLCSP結構導線之可靠度分析，本文設計了四種繞線形式做為探討，並以驗證之模擬流程搭配全域局部有限元素分析法進行研究。從模擬結果中會發現應力應變主要集中於晶片接出導線(Via)、晶片及EMC交接面(Interface)附近以及接入墊片導線(Pad Junction)，且得出各式繞線設計的可靠度分析。
本文研究之FO-WLCSP結構中使用EMC作為晶片周遭的填充物，並利用它將封裝接腳散到更大的面積上，但EMC吸收水氣後會與其他材料的黏著度降低，進而在製程或是可靠度測試時產生脫層影響封裝的可靠度。而於脫層對導線可靠度的影響中，本研究中探討了數個主要的脫層參數，瞭解脫層確實對導線可靠度有深遠的影響。
本研究對於導線可靠度分析的結果，可套用於結構相近之WLP、CSP、WLCSP中使用，做為封裝繞線設計之參考。

In recent years, the quality demand on electronic components keep on growing while functionality and efficiency of electronic products get stronger. The structure of electronic packaging also developed from conventional DIP (Dual In-line Packaging), SOP/TSOP (Small Outline Packaging / Thin Small Outline Packaging), QFP/TQFP (Quad Flat Packaging / Thin Quad Flat Packaging) and BGA(Ball Grid Array) to small volume and high density package such as Flip Chip, CSP(Chip Scale Packaging), WLP (Wafer Level Packaging), FO-WLCSP(Fan-Out Wafer Level Chip Scale Packaging), System-in-Packaging(SiP), etc.
Many research works found that traditional WLP shows poor solder joint reliability during thermal cycling, so researchers derived a methodology to resolve it. Forming a stress buffer layer under solder ball is the most acceptable and effective method. However, it was still found out that the large deformation of stress buffer layer caused reliability issue of trace line. So in this research, we discuss reliability of trace line in our FO-WLCSP structure after thermal cycling test.
It is time-consuming and labor-intensive to carry out research in an experimental way and the cost is higher, too. Therefore, we use simulation approach to carry out our research. In order to ensure the simulation feasibility, we built the FO-WLCSP structure model designed by Yew [17] at first. After finishing the model we validated our result by Yew’s and it had good agreement with experimental data. So we could assure the accuracy of the simulation process.
To study the reliability of trace line in FO-WLCSP structure, four kinds of trace line routing patterns are designed and discussed in this paper. The modeling process being validated and global-local finite element analysis method will be adopted to our modeling. From the simulation results, it is found that the stress and strain are mainly concentrated at via, interface and pad junction.
The FO-WLCSP structure studied in this paper uses EMC as a filler around the chip and uses it to fan out the I/Os to a larger area. However, the adhesiveness of EMC to other materials will decrease after absorbing moisture. Thus, the delamination caused by the fabrication process or reliability test affects the reliability of the package. For the influence of delamination on the trace line reliability, several major delamination parameters were explored in this study. After the research, we realize that delamination does have a profound effect on the trace line reliability.
From the outcomes of this study, the results of trace line reliability analysis can be applied to WLP, CSP and WLCSP with similar structure, and can be used as a reference for package trace line routing design.

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