應用於雙極性電晶體選擇器電阻式隨機存取記憶體之熱察覺感測電路

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研究生：	郭家辰 Kuo, Chia-Chen
論文名稱：	應用於雙極性電晶體選擇器電阻式隨機存取記憶體之熱察覺感測電路 A Thermal Aware Current Sensing Circuit for RRAM using BJT selector
指導教授：	張孟凡 Chang, Meng-Fan
口試委員:	洪浩喬 Hong, Hao-Chiao 邱瀝毅 Chiou, Lih-Yih
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	63
中文關鍵詞：	雙極性電晶體、電阻式隨機存取記憶體、熱察覺、感測電路
外文關鍵詞：	BJT, RRAM, Thermal Aware, Sense Amplifier
相關次數：	點閱：3 下載：0
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手持式消費性電子產品、智慧型車用電子等產品需要非揮發性記憶體做程式的儲存。而產品要達到高效能與快速回應的目標，對於執行程式將有高速讀取的需求。藉由非揮發性內嵌式記憶體與微控制單元(MCU)整合，可成功大大提高MCU之高速資料處理速度。
目前傳統的內嵌式記憶體都使用快閃記憶體，然而快閃記憶體(Flash memory)有讀取與寫入速度慢，寫入操作無法直接寫入(需要block erase)，並需要高電壓。製程縮小至奈米等級之後，快閃記憶體在微縮上遇到了許多物理限制，使其成本上升或是特性劣化。因此開發新型態非揮發性記憶體是必需且迫切的。電阻式記憶體(RRAM)為公認相當具有潛力取代快閃記憶體，如給予適當的寫入驅動電流，其可達到快速直接寫入、低寫入電壓與低功耗、具有快速讀取度、寫入阻值均勻穩定並可在長時間儲存後擁有穩定而不漂移的阻值等優點。
電阻式記憶體目前面臨兩個主要的挑戰:
1. 滿足寫入驅動電流的要求並減小驅動電晶體的面積來提高密度
2. 加大讀取電流提高資料讀取良率與讀取速度的同時避免讀取干擾
在此篇論文中，我們使用了與CMOS製程相容的創新之寄生BJT元件，可節省4.5倍以上的面積。但BJT驅動能力對溫度具有較高的敏感度，若是以傳統箝制電路將位元線電壓固定，在高溫時即可能因溫度升高而造成讀取干擾的問題。而若是以預留邊限(margin)改變箝制電壓使傳統箝制電路在高溫時不會讀取干擾，則在低溫時讀取電流將下降並影響良率。
因此我們提出具溫度警覺位元線偏壓讀取機制(Temperature-Aware Bit-line Bias Scheme)來解決BJT溫度變異的問題。此機制在低溫下可提高4.7倍的細胞電流，配合具溫度警覺之加速機制可提高1.6倍的讀取速度。
我們分別以0.18微米與65奈米製程實作1Mb與2Mb的BJT RRAM記憶體測試晶片。量測結果其讀取速度可達到4.2ns and 4.7ns, 為目前全世界Mb等級RRAM晶片中最快的速度表現。

Handheld electronics, car electronics, and portable biomedical electronics require nonvolatile memory for code storage. In order to achieve high performance operation, fast program code access for microcontroller unit (MCU) is prerequisite. By integrating embedded memory with MCU, higher processing performance can be achieved.
Flash memory is the mainstream embedded nonvolatile memory. However, Flash memory cannot achieve high speed write operation due to sequential write。It also requires high voltage (>10V) to perform write operation。Furthermore, it is difficult to scale down Flash in deep nanometer scale. Thus, the research and development of emerging nonvolatile memory is necessary and becoming popular topic. Among those emerging memories, Resistive Random Access Memory (RRAM) is one of the most promising candidates. It has attractive characteristics such as low write voltage, fast write speed, low write energy, and good retention time.
However, two major challenge should be solved for RRAM:
1. Reducing the area of cell select switches, while satisfying write current requirements.
2. Maximizing ICELL for yield and speed, while maintaining a small voltage drop across the RRAM device (VR) to prevent read disturbance.
In this work, a logic process compatible vertical parasitic BJT (VPBJT) is used to reduce the macro area. Comparing to CMOS array, the VPBJT can achieve 4.5X smaller macro area. However, BJT is sensitive to temperature variation which affects read reliability. We propose a thermal-aware bitline (BL) voltage bias scheme (TABB) for current-mode read with 4.7x larger cell current, and a 1.6x faster read speed.
We fabricated 0.18μm 1Mb and 65nm 2Mb VPBJT RRAM macros to confirm the efficacy of the proposed sensing scheme. 4.2ns and 4.7ns access time have been measured for 0.18μm and 65nm macro respectively, which is the fastest random read speed among reported Mb-scaled NVM macros.

摘要    i
Abstract    iii
致謝    v
Contents    vi
List of Figures    viii
List of Tables    xi
Chapter 1    Introduction    1
1.1    The Memory Landscape    2
1.2    Scaling Challenges of Flash Memory    3
1.3    Emerging Non-Volatile Memory    7
1.4    Applications of RRAM    10
Chapter 2    BJT-selected RRAM    12
2.1    Vertical Parasitic BJT (VPBJT)    14
2.2    RRAM Cell    17
2.2.1    Structure of RRAM Cell    17
2.2.2    Switching Mechanism    18
2.2.3    Cell Operations    18
Chapter 3    Proposed Sensing Scheme    24
3.1    Design Challenge of BJT-selected RRAM    24
3.1.1    RRAM disturb issue    24
3.1.2    BJT variation    25
3.2    Previous Work    27
3.3    Proposed Sensing Scheme    29
3.3.1    VBE-Tracking Unit and Thermal-Aware Bitline Clamper    32
3.3.2    Two-Step Bitline Self-Bias (TBLSB) Scheme    34
Chapter 4    Analyses and Comparisons    37
4.1    Temperature variation effect    37
4.2    Read Speed Improvement    39
4.3    Area and Power Overhead    40
Chapter 5    Macro Implementation    43
5.1    BJT RRAM Macro    43
5.2    Memory Array Structure    45
5.3    Design for Test    47
Chapter 6    Experimental Result and Conclusion    49
6.1    Performance Measurement    50
6.2    Conclusions and Future Work    52
References    56

                                

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