As the number of processor on a single chip grows, communication efficiency may dominate the performance of parallel programming. Seeking for high throughput communication is a clear goal. In this paper, a novel 4-stage pipelined router is proposed for 3-stage Clos network and its corresponding network interface (NI). The proposed structure is built in DE3 and the performance is estimated using an in-house C++ simulator. To further improve the throughput, we propose a late release scheme (LRS) which reserves the allocated paths. The simulation result shows the throughput improvements are 9.42% and 42.91% under random and mixed traffic, respectively. The latency improvements are 5.1 and 2.53 under Jacobi linear equation simulation with 1k and 512 data sizes, respectively.

隨著單晶片中運算核心數目的成長，之間通訊效率漸為平行程式能的關鍵。找尋低延遲通訊方法儼然成為大家目標本篇論文提供了有效率multicast的Clos交換器管線化電路與其對應的傳收介面，此外我們利用時間的介面，此外我們利用時間的介面，此外我們利用時間的介面，此外我們利用時間的介面，此外我們利用時間的局部性進一步縮短傳輸的延遲，並提出延遲清除路徑的概念與其實現方法。
本論文以Altera DE3Altera DE3驗證功能性，並以驗證功能性，並以驗證功能性，並以C++作效能的評估。改進架構在作效能的評估。改進架構在作效能的評估。改進架構在Jacobi Jacobi Linear Equation Solver與一些合成的通訊都顯現出較低傳遞延遲與最大傳輸量的提升。

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