適用於多標準正交分頻多工系統之平行快速傅立葉轉換處理器

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研究生：	羅智羽 Chih-Yu Lo
論文名稱：	適用於多標準正交分頻多工系統之平行快速傅立葉轉換處理器 A Parallel FFT/IFFT Processor for Multi-Standard OFDM Communications
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	中文
論文頁數：	中文(13) 英文(93)
中文關鍵詞：	正交分頻多工、抗載波間干擾、符元間干擾、快速傅立葉轉換處理器、反快速傅立葉轉換處理器、平行處理、可重組化、可程式化邏輯陣列
外文關鍵詞：	OFDM, ISI, ICI, FFT, IFFT, Parallel processing, Reconfigurable, FPGA
相關次數：	點閱：3 下載：0
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近年來正交分頻多工系統 (OFDM) 被廣泛的應用在無線區域網路上，主要其優點為有效對抗載波間干擾 (Inter-Carrier Interference) 與符元間干擾 (Inter-Symbol Interference)，並增加通道頻帶的利用率。其中快速傅立葉轉換處理器 (FFT) 為實現OFDM系統的核心，因此在這篇碩士論文中，我們設計一個低複雜度及高效率並可適用於多種OFDM標準系統之平行FFT/IFFT處理器。

由於不同OFDM標準的系統具有相似的硬體架構，我們藉由增加些許硬體以提高此FFT/IFFT處理器之利用性。在演算法上，我們採用radix-2/4/8來減少算術複雜度及硬體所需的複數乘法器。而在硬體實現上，我們採用三個實數乘法器之複數乘法器和八分之一週期twiddle factor儲存技術來簡化所需的硬體。為了提高此FFT/IFFT處理器之效能，我們提出一個改良的信號流程圖以適用於平行處理上。使得一個大點數的傅立葉轉換分解成幾個小點數的傅立葉轉換平行運算來取代以加速運算時間。由於使用平行處理架構，在記憶體模組上會有大量的需求，這會造成面積增加及功率損耗上升。因此，我們利用multi-word length的儲存方法以改善這種負面效應。

最後，根據上述所提到之技術，我們使用Xilinx Spartan3來實現一顆可執行8K、4K、2K、1K、256及64點的FFT/IFFT處理器。而這顆FFT/IFFT處理器採用4階層的平行處理架構，並包含24個複數乘法器及7個雙埠記憶體模組。在使用序列資料輸入及平行資料運算下，這顆FFT/IFFT處理器可操作於200MHz。因此也可以廣泛的應用於高速信號處理上。

關鍵字：正交分頻多工系統(OFDM), 抗載波間干擾(ICI), 符元間干擾(ISI), 快速傅立葉轉換處理器(FFT), 反快速傅立葉轉換處理器(IFFT), 平行處理(parallel processing), 可重組化(reconfigurable), 可程式化邏輯陣列(FPGA)

Orthogonal Frequency Division Multiplexing (OFDM) is a popular advanced communication technology for wireless local area network (WLAN) because it can effectively improve channel utilization and reduce inter-symbol interference (ISI) and inter-carrier interference (ICI) caused by multipath effect. Since FFT and IFFT is a core of OFDM technique, we design a low hardware complexity and high performance FFT/IFFT processor for multi-standard OFDM communications in this thesis.

Because hardware requirement of various communication systems based on OFDM have similar architectures, we can add little extra hardware to improve the flexibility of hardware usage. In algorithms, we adopted radix-2/4/8 algorithm to reduce computational complexity and minimize required complex multipliers. In hardware implementation, we used three real multipliers to implement a complex multiplier and storage technique of eighth sine/cosine values in order to simplify required hardware. We also proposed a modified signal flow graph to be suitable for parallel processing, and then it can improve the performance of FFT/IFFT processor. Because of using parallel processing architecture, it required a lot of memory banks to cause large area and power consumption. Therefore, we utilized the multi-word length storage technique to minimize required memory banks.

At finally, we used a Xilinx Spartan3 board to implement an 8k/4k/2k/1k/256/64-point FFT/IFFT processor. This processor consisted of 4-level parallel architecture、24 complex multipliers and 7 dual-port SRAM. The proposed structure can operate at 200MHz, and will be applied widely in high-speed signal processing.

  Introduction                                                   1
1    Background.............................................................................................1
2    Motivation……………………………………………………….………...2
3    Organization of the Thesis………………………………….…………...3

  FFT Algorithms                                                5
1    Decimation-in- Algorithms……………..…………………………………..9
2    Decimation-in-Frequency FFT Algorithms……………………………….9
2.1    Fixed-Radix FFT Algorithms………………………………………...9
2.1.1    Radix-2 DIF Algorithm…………………………………….9
2.1.2    Radix-4/Radix- DIF FFT Algorithm…………………….13
2.1.3    Radix-8/Radix- DIF FFT Algorithm…………………….17
2.2    Split-Radix FFT Algorithms…………………………………………21
2.2.1    Radix-2/4 DIF FFT Algorithm………………………….….22
2.2.2    Radix-2/8 DIF FFT Algorithm…………………….……….24
3    Comparison and Summary……………………………………………….27

  FFT Architectures                                             29
1    Architectures Overview……………………………….………………..29
2    Pipeline Architectures……………………………….………………….30
2.1    Introduction………………………………………………………..30
2.2    Single-Path Delay Feedback Pipeline Architecture………………….31
2.3    Multi-Path Delay Commutator Pipeline Architecture……….…....….37
3    Comparison and Summary…….………………………………………….40

  A Parallel and Reconfigurable FFT/IFFT Processor          43
1    Radix-2/4/8 Algorithm……………………………………………………43
1.1    Complex Multiplications by  …………………………..43
1.2    Radix-2/4/8 Algorithm………………………………………………45
2    Parallel FFT Algorithm……………………………………………….…..48
3    Reconfigurable Length FFT/IFFT Processor Architectures……….……..55
4    Comparison………………………………………………………………58

  Circuit Design                                                61
1    Fixed-Point Simulation…………………………………………………..61
2    Butterfly………………………………………………………………….71
2.1    Radix-2/4 Butterfly………………………………………………….71
2.2    Radix-2/4/8 Butterfly………………………………………………..73
3    Multiplier…………………………………………………………………75
3.1    Constant Multiplier…………………………………………………..75
3.2    Complex Multiplier………………………………………………….76
4    Serial to Parallel & Parallel to Serial Converter………………………….78
4.1    Serial to Parallel Converter………………………………………….78
4.2    Parallel to Serial Converter………………………………………….79
5    FIFO Using SRAM……………………………………………………….79
6    ROM Table………………………………………………………………..80
7    Simulations and Measurements………………………………………..….83
7.1    SystemC and Verilog Simulations…....................................................83
7.2    FPGA Measurements…………………………………………………85

  Future Works and Conclusions                                89
1    Future Works………...……………………………………………….89
2    Conclusions……………………………………………………...……89

                                

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