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研究生: 李明澤
Li, Ming-Ze
論文名稱: 用於植入式裝置中讀取神經訊號的低雜訊放大器
A Low-Noise Amplifier for Implantable Device for Neural Signal Acquisition
指導教授: 鄭桂忠
Tang, Kea-Tiong
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 99
語文別: 中文
論文頁數: 99
中文關鍵詞: 植入式裝置低雜訊放大器
外文關鍵詞: Implantable Device, Low-noise Amplifier
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  • 隨著科技的進步與人類對於健康管理的需求,工程科學與生物醫學的結合發展將帶給人們便利與許多新的契機。人體植入式晶片的應用,即是半導體科技與生物醫學的結合產物。關於植入式裝置的研究有相當多,包括了矽耳蝸、人工視網膜、以及帕金森氏症等等。這些裝置植入人體後,人們會想要知道這些部位的神經活動或是刺激後的神經所產生的訊號反應,並且加以記錄。同時,觀測並記錄神經細胞的活動電位對於閉迴路控制的深層腦刺激是相當中要的,例如像是在癲癇或是帕金森氏症的治療中。
    植入式晶片的信號讀取最前端是陣列式電極,此種電極所能夠讀取到的信號是既微小(10μV-200μV)又低頻(0.1Hz-10kHz)的胞外信號。不幸的是,MOSFET製程在低頻帶天生就有很大的低頻雜訊,這會造成胞外信號讀取的SNR相當差。
    當植入式裝置讀取神經訊號時,微電極與人體體液接觸面所產生的偏差電壓將可以很容易得使得放大器飽和。為了解決這個問題,在前端放大器加上了負回授電阻以及電容形成高通濾波以濾除值流偏差電壓。然而,此高通濾波的轉角頻率必須低於0.1Hz的神經訊號,所以通常需要很大的電容或電阻去實現,這會浪費很多面積。於是,在本研究論文採用MOS電阻取代了巨大面積的電阻。
    在HPF後方的前端放大器採用了全差動OTA的型式。筆者認為,操作在適度反轉區的電晶體比弱反轉區要來得好。將前端放大器的輸入差動對操作於適度反轉區,同時將其他電晶體操作於高度反轉區並且設計成長通道元件;這可以使得輸入差動對主宰前端放大器的熱雜訊、閃爍雜訊以及偏差電壓,並且避開弱反轉區中閃爍雜訊以及偏差電壓上升的現象。此外,由於所使用的製程中PMOS的閃爍雜訊能量隨通道反轉程度上升的幅度相當可觀,因此在前端放大器中,使用了操作在深歐姆區的電晶體當作PMOS的源極鈍化以降低PMOS閃爍雜訊的貢獻。在前端放大器之後,則是以一個一階的gm-C濾波器過濾不要的高頻雜訊。
    測量的結果顯示了,這個以TSMC 1P6M 0.18μm製程製作的放大器在0.1Hz-10 kHz的頻寬範圍內等效輸入雜訊為5.62μVrms,前端放大器的功率消耗為14.2μW,NEF為7.45,增益、CMRR、PSRR則分別為49.5dB、70dB以及57dB。


    Much research is being done on implantable devices, such as cochlear implants, retinal prostheses, motor prostheses, etc. Acquiring information regarding the stimulated neurons and recording the neural activities in these neural prosthetic devices is essential. It is also crucial to monitor and process the neural action potential signals in real time for closed-loop controlled deep brain stimulation (for example, in epilepsy and Parkinson’s disease).
    The front end of the implantable device is an array of stimulating/recording electrodes. These electrodes read extracellular neural signals (ENG), which are very small (10μV-200μV) and have a low frequency (0.1Hz-10kHz), requiring a low-noise amplifier (LNA) for signal amplification to acquire the neural signal. Unfortunately, MOSFET process has inherent 1/f noise that dominates at low frequencies, while ENG is in the same frequency band as 1/f noise, resulting in a very poor SNR.
    When reading the neural signals in an implantable device, the DC offset of the tissue-electrode interface can easily saturate the amplifier. To solve this problem, feedback capacitors and resistors are connected to the preamp to form a high pass function to filter the DC offset. The corner frequency of this HPF has to be lower than 0.1Hz, which requires a very huge capacitor/resister to implement. A MOSFET resistor is used to provide an area-efficient means of creating a large resistance.
    Behind the HPF, a fully differential OTA is used to implement the preamp. EKV model is used for analysis because the transistors are operated in different inversion levels. The input transistors of the preamp are operated in modereate inversion, while non-input transistors in higher inversion level and long channel, so that the input stage will dominate the thermal noise, 1/f noise and offset contribution. Transistors operated in deep trode region are used as source-degenerated resistors to lower down the trans-conductance of PMOS operated in strong inversion, while the PSD of 1/f noise get higher with inversion level of PMOS in the process we used. Behind the preamp, a gm-C first order filter removes the high-frequency noise carried in the unwanted band.
    Measurement results shows the input-referred noise of the system is 5.62μVrms from 0.1Hz to 10 kHz, power consumption of preamp is 14.2μW, NEF is 7.45, the gain is 49.5dB, CMRR is 70dB and PSRR is 57dB. The amplifier was fabricated using a TSMC 0.18μm 1P6M CMOS process.

    摘 要 i ABSTRACT ii 致 謝 iii 目 錄 iv 圖目錄 vii 表目錄 x 第一章 緒論 1 1.1 研究動機-植入式裝置介紹 1 1.2 文獻回顧 3 1.2.1 截波穩定式放大器 3 1.2.2 感應放大器 4 1.2.3 前饋式偏差電壓消去 6 1.2.4 偽開迴路架構 7 1.2.5 電容耦合、閉迴路架構 7 1.3 系統規格 9 第二章 雜訊、元件雜訊特性與雜訊效能指數 11 2.1 雜訊簡介 11 2.2 設計過程中所需考量的MOS雜訊 12 2.2.1 熱雜訊 12 2.2.2 閃爍雜訊 14 2.2.3 散射雜訊 21 2.2.4 其他相關雜訊 22 2.3 雜訊效能指數 25 第三章 LNA設計原理 27 3.1 適度反轉區以及EKV模型 27 3.1.1 等效閘-源電壓差(VEFF) 28 3.1.2 汲-源飽和電壓差(VDSAT) 28 3.1.3 本質增益 29 3.1.4 本質頻寬 30 3.1.5 熱雜訊 31 3.1.6 閃爍雜訊 32 3.1.7 不匹配造成的偏差電壓 32 第四章 LNA架構與設計流程 37 4.1 LNA系統架構 37 4.2 HPF電路實現 38 4.3 Preamp電路架構 41 4.3.1 直流輸入、輸出範圍 43 4.3.2 增益 44 4.3.3 頻寬 45 4.3.4 熱雜訊 46 4.3.5 閃爍雜訊 49 4.3.6 不匹配造成的偏差電壓 52 4.4 LPF 電路架構 56 4.5 輸出緩衝器電路架構 58 第五章 電路模擬與佈局 61 5.1模擬結果 61 5.1.1 Preamp 開迴路模擬 61 5.1.2 Preamp 閉迴路模擬 62 5.1.3 LPF模擬 63 5.1.4 LNA模擬 64 5.1.5 Buffer模擬 65 5.2電路佈局 67 第六章 量測結果分析與討論 70 6.1 晶片連續性量測(continuity testing)配置與結果 70 6.2 閉迴路增益量測配置與結果 71 6.3 雜訊量測配置與結果 77 6.4 CMRR量測配置與結果 79 6.5 PSRR量測配置與結果 79 6.6 偏差電壓量測配置與結果 82 6.7 SNR量測結果 83 6.8 模擬神經訊號量測實驗 83 6.9 結合電極量測實驗 84 6.10量測結果以及相關文獻比較 86 6.11量測結果討論 88 第七章 結論 90 7.1結論 90 7.2未來工作 91 參考文獻 92

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