在通訊技術的更迭中，4G的通訊技術使得訊號可以擁有快速的傳輸速度，使得原本3G無法實現的應用一一實現，例如:視訊通話以及高速傳輸。為了實現這些應用，類比數位轉換器在系統中是不可被取代的一部份，類比數位轉換器可以將類比訊號有效的轉為數位訊號，而現今有著不同架構以及不同類型的類比數位轉換器，其中連續漸進式類比數位轉換器是較為流行的，其中的原因為數位電路的部分較多較容易藉由製成的演進而簡化，另外一部份的原因為電路架構優秀的擴充性讓連續漸進式類比數位轉換器受到較多的青睞。
本論文實現一個連續漸進式類比數位轉換器並以帶冗餘位的方式優化切換上的速度使得速度能夠進一步的提升。此連續漸進式類比數位轉換器有著高速度低功率的特性，可以用於時序交錯的類比數位轉換器並可再加上通道並聯的架構讓速度的到進一步的提升。
本論文的架構使用台積電65奈米的製程來設計，操作電壓為1.2伏特，峰對峰值的輸入訊號為2.2伏特，在模擬結果的有效位元數為9.902，DNL為+0.02/-0.24，INL為+0.23/-0.24，平均消耗功率為2.800572244mW，電路面積為0.0254〖mm〗^2。

Abstract(英文摘要)

In the change of wireless communication technology, 4G technology provide high transmission speed for signal. ADC are an irreplaceable part of the system and it can effectively convert analog signals into digital signals. Nowadays, there are different types of ADCs. Among them, SAR ADC are more popular because in SAR ADC many digital circuits are easier to simplify by the evolution of technology scales.
This paper implements a successive-approximation ADC and optimizes the switching speed with redundancy so that the speed can be further improved. This SAR ADC has the characteristics of high speed and low power. It can be used in the timing-interleaved ADC and can be coupled with a parallel channel architecture to further increase the speed.
The SAR ADC is implemented in TSMC 65nm process. The supply voltage is 1.2 volts, the peak-to-peak input signal is 2.2 volts, the number of effective bits in the simulation results is 9.902, the peak DNL value is +0.02 to -0.24 LSB and the peak INL value is +0.23 to -0.24 LSB, the average power consumption is 2.801mW, and the circuit area is 0.0254. 〖mm〗^2。

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