中文摘要
在本篇研究裡，提出了可以同時正向與反向離散餘弦轉換(Discrete Cosine
Transform)。利用我們所提出的排序與時間交錯的方法，可以達到低成本和高輸出量。在一般傳統的影像編碼系統中，正向與反向DCT必須要同時運行，才可以滿足即時(Real-Time) 影像編碼，所以本篇所提出的架構可以滿足同時運行DCT 與IDCT，且本篇有三個主要的優點，第一，本篇所提出的架構可以同時運行DCT 與IDCT這兩個轉換，第二，本篇可以滿足即時影像編碼系統的需求，第三，本編所提出的排序與時間交錯的方法可以達到低成本與高輸出量，藉由需要一個一維DCT與IDCT電路與轉制記憶體(Transpose Memory)就可以達到同時運DCT 與IDCT的效果。本篇所提出的架構可以支援MPEG-1/2/4的影像壓縮標準與滿足IEEE IDCT 1180-1990的精確度標準，採用TSMC 0.18-um 1P6M CMOS 技術；而在量測結果中顯示了當運行在同時正向與反向DCT的模式下最大的時脈(Clock)可以達到200MHz，而且面積包含19.65K的邏輯閘和最大的輸出量可以達到400Mpixel/sec；由於在本篇整個的設計裡，僅需要一個一維的DCT/IDCT電路和轉制記憶體(Transpose Memory)，就可以達到同時計算於DCT和IDCT的一維與二維資料流和同時計算於DCT 與IDCT轉換，並且利用本篇提出的方法，可讓Register 使用度達到100%，且本篇所提出的硬體，可支援於即時(Real-Time)影像系統HDTV(1920×1080P@60HZ)的規格。

Abstract
In this thesis, the proposed simultaneous forward and inverse discrete cosine transform (DCT) core exploits sorting and butterfly method that can be cost-efficient implemented. In real-time video encoder, the forward and inverse transforms are needed to be executed simultaneously. The proposed architecture has three advantages: First, multi-function work in DCT/IDCT can be simultaneously computed. Second, it can support real-time system in video encoder. Third, it exploits sorting and butterfly method by only one 1-D core and a transpose memory (TM), which can simultaneously compute two types of DCT and IDCT. Supporting MPEG-1/2/4 standards in video format as well as IEEE IDCT standard precision, the proposed design is implemented in a TSMC 0.18-um 1P6M CMOS technology. Measurement results show clock rate of 200M/sec while operated in simultaneous forward and inverse DCT mode and resultant circuit includes 19.65K logic gates with maximum throughput rate of 400Mpixel/sec. The proposed architecture can support HDTV video (1920×1080P@60 HZ) requirement operated in real-time video encoder.

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